Kimberly P. Ellis

Component allocation to balance workload in printed circuit card assembly systems

Component allocation in printed circuit card assembly systems is a special case of the classical mixed-model assembly line balancing problem and involves assigning component types to machines to achieve specific production objectives. In this paper the component allocation problem is considered for the scenario where there are two or more placement machines (possibly nonidentical) and the objective is to balance, for every card type, a combination of the card assembly time and the machine setup time. A mathematical formulation of the problem is developed for a class of placement machines. Two alternative solution approaches are presented: a list-processing-based heuristic for a simple version of the problem, and a linear-programming-based branch-and-bound procedure for the general component allocation problem. Industrial case study results are presented for each approach that indicate expected throughput improvements of up to 8--10% over the companys current procedure, with much less direct effort required by the process engineer.

Optimizing the performance of a surface mount placement machine

Process planning is an important and integral part of effectively operating a printed circuit board (PCB) assembly system. A PCB assembly system generally consists of different types of placement machines, testing equipment, and material handling equipment. This research develops a new solution approach to determine the component placement sequence and feeder arrangement for a turret style surface mount-placement machine often used in PCB assembly systems. This solution approach can be integrated into a process planning system to reduce assembly time and improve productivity. The algorithm consists of a construction procedure that uses a set of rules to generate an initial component placement sequence and feeder arrangement along with an improvement procedure to improve the initial solution. An industrial case study conducted at Ericsson, Inc., using a Fuji CP4-3 machine and actual PCB data, is presented to demonstrate the performance of the proposed solution approach. The solutions obtained using the proposed solution approach are compared to those obtained using state of the art PCB assembly process optimization software. For all PCBs in the case study, the proposed solution approach yielded lower placement times than the commercial software, thus generating additional valuable production capacity. This research is applicable for both researchers and practitioners in printed circuit board assembly systems.

Development and application of a worker assignment model to evaluate a lean manufacturing cell

In lean manufacturing environments, cross-training is often used to achieve multi-skilling in order to increase flexibility in meeting fluctuating demand, to create a shared sense of responsibility, and to balance workload between cross-trained workers. This paper presents a model that assigns workers to tasks within a lean manufacturing cell while minimizing net present cost. In determining how to assign workers to tasks, the model addresses production requirements to meet customer demand, skill depth requirements for tasks, varying quality levels based on skill depth, and job rotation to retain skills for a cross-trained workforce. The model generates an assignment of workers to tasks and determines the training necessary for workers to meet skill requirements for tasks and customer demand. While the model can be used in a number of ways, in this paper it is used to generate a worker assignment schedule for cross-trained workers in a dedicated lean manufacturing cell in an electronics assembly plant and to evaluate the effect of increased cross-training on the cell. The resulting worker assignment schedules for the current state and several alternative scenarios for the cell are evaluated using cost results from the optimization model and from a simulation model to assess additional performance metrics. These results demonstrate the usefulness of the worker assignment model and indicate that moderate increases from current cross-training levels are not beneficial for this cell.

Scheduling of wafer test processes in semiconductor manufacturing

This research focuses on solving a common wafer test scheduling problem in semiconductor manufacturing. During wafer testing, a series of test processes are conducted on wafers using computer-controlled test stations at various temperatures. The test processes are conducted in a specified order on a wafer lot, resulting in precedence constraints for the schedule. Furthermore, the assignment of the wafer lots to test stations and the sequence in which they are processed affects the time required to set up the test operations. Thus, the set-up times are sequence dependent. Four heuristics are developed to solve the test scheduling problem with the aim of minimizing the makespan required to test all wafers on a set of test stations. The heuristics generate a sorted list of wafer lots as a dispatching sequence and then schedule the wafer lots on test stations in order of appearance on the list. An experimental analysis and two case studies are presented to validate the proposed solution approaches. In the case studies, the heuristics are applied to actual data from a semiconductor manufacturing facility. For both case studies, the proposed solution approaches decrease the makespan by 23–45% compared with the makespan of the actual schedule executed in the manufacturing facility.

A structured approach for assessing the effectiveness of engineering design tools in new product development

Abstract: This article presents an approach for assessing the effectiveness of engineering design tools applied within new product development (NPD). In this approach both the quality of the process used to apply the design tool and the quality of outputs generated by the design tool are assessed. The approach described was developed and piloted in an engineer-to-order (ETO) company. The specific assessment instruments created are also presented. Future work will include investigating the use of the approach for additional design tools and analyzing how design tool effectiveness relates to overall product launch effectiveness.

Optimization of the assignment of circuit cards to assembly lines in electronics assembly

Process planning is an important and integral function for ensuring efficient operations in printed circuit card assembly systems. This paper presents a new approach for solving the circuit card to assembly line assignment problem to minimize assembly time. This problem occurs frequently in process planning for electronic assembly systems and involves considering other interelated process planning problems. The line assignment problem is formulated as a large-scale mixed-integer programming problem and then solved using problem decomposition along with the branch-and-bound algorithm. Techniques for improving the solution time are discussed, and the solution approach is demonstrated using industry representative data sets from Lucent Technologies. For the data sets considered, the solution approach provides solutions within 3% of optimal in approximately 6 min of computation time on a Sun UltraSparc 2 Workstation. The solution approach developed for addressing the line assignment problem can serve as a useful decision-support tool by offering significant opportunities to improve the productivity and throughput of the assembly lines with improved process plans. The approach also allows planning engineers to respond faster to changes in production requirements. This research will be of interest to researchers in printed circuit card assembly systems and to practitioners in both original equipment manufacturing and contract assembly firms.

Development of a placement time estimator function for a turret style surface mount placement machine

Abstract Efficiently placing printed circuit board (PCB) components is critically important in the highly competitive electronics industry. Previous research has focused on algorithms to determine feeder arrangement and placement sequencing for placement machines. However, consistent machine models do not exist that can be used to compare the results of these algorithms. A conceptual model of a placement time estimator function is constructed for turret style surface mount technology (SMT) placement machines. Empirical data is then used to develop the estimator function for the Fuji CP4-3 machine. Results for eight commercial PCB designs indicate that there is no statistical difference between the actual and the estimated placement times. Thus, the placement time estimator function developed in this research provides an accurate method to estimate component placements times on a PCB by a Fuji CP4-3. The placement time estimator function presented here can be used as part of a computer integrated manufacturing system to facilitate process planning and improve cycle time estimates for production planning purposes.

The Impact of Standardized Metric Physical Internet Containers on the Shipping Volume of Manufacturers

Abstract One of the key aspects of the Physical Internet (PI) is the use of standardized, modular containers that enable the coordination of shipments across the supply chain. However, a key open question is how will limiting the choice of containers impact the amount of volume that is shipped? We present a mathematical model to determine that impact and report our results for data sets that are based on data from a consumer packaged goods company.

Effective material flow at an assembly facility

Effective material flow in an assembly facility leads to reduced material handling costs and increased productivity. This research focuses on improving the flow of materials for an assembly facility that receives supplied parts through receiving docks and transfers the parts to material storage locations and then to part usage locations. The locations of the receiving docks, storage locations, and line locations are predetermined, but the assignment of parts to dock locations and storage locations and the material flow paths through the facility are decision variables. Furthermore, design decisions such as the dock strategy employed and the configuration of the storage areas lead to additional decision variables. The goal is to reduce overall material handling costs by effectively receiving, storing and transferring the material from loading docks to line locations. The contribution of this research is in applying multi-commodity network flow models that integrate many of the sub-problems that are assumed to be solved a priori in many existing models. This integrated approach was used to evaluate configuration changes for a collaborating facility. One of the scenarios analysed showed an improvement in the material handling costs of nearly 10% as compared to current practices.

Improving throughput for an electronic assembly line using a constraint analysis methodology

Electronic assembly operations are vital to industries such as telecommunications, computers and consumer electronics. This paper presents a constraint analysis methodology for planning and improving electronic assembly operations that draws on concepts from queueing theory, simulation and production planning. The proposed methodology identifies the operational bottleneck and predicts the utilization, throughput and lead time of the assembly line. It also quantifies the relationship between yields and utilization for the assembly operations. A case study is presented that applies the methodology at an Ericsson, Inc., telecommunications equipment assembly facility. The constraint analysis methodology provided valuable decision support as the managers of Ericsson evaluated the costs and benefits of additional production capacity. Although the focus of this paper is electronic assembly operations, the methodology can be applied to general flow line assembly systems with feedback loops for test and rework under dedicated high-volume production.