King Ho Tam

Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random leff variation

This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic variation and random channel length (Leff) variation of transistors on interconnect design. We first construct a table look-up based interconnect RC parasitic model considering CMP effects with optimized fill insertion. Based on the model, we solve the simultaneous buffer insertion, wire sizing and fill insertion (SBWF) problem under CMP variation. We also extend the SBWF problem to consider the random Leff variation (SBWF). We approach the resulting vSBWF problem by (1) incorporating probability density function (PDF) into the SBWF algorithm; and (2) developing an efficient heuristic for PDF pruning, whose practical optimality is verified by an accurate but much slower pruning. Experimental results show that the SBWF design improves timing by 1.0% and reduces power by 5.7% on average with 7.4% less buffer area over the conventional buffer insertion and wire sizing design followed by fill insertion (SBWF), and that the vSBWF design reduces yield loss due to CMP and Leff variations by 44.3% on average over the SBWF design. The runtime of vSBWF is 8.3x that of SBWF, and vSBWF for the largest example containing 3103 sinks finishes in 124 minutes.In this paper, we present a completely new approach to the problem of delay minimization by simultaneous buffer insertion and wire sizing for a wire. We show that the problem can be formulated as a convex quadratic program, which is known to be solvable in polynomial time. Nevertheless, we explore some special properties of our problem and derive an optimal and very efficient algorithm to solve the resulting program. Given m buffers and a set of n discrete choices of wire width, the running time of our algorithm is O(mn^2) and is independent of the wire length in practice. For example, an instance of 100 buffers and 100 choices of wire width can be solved in 3 seconds. Besides, our formulation is so versatile that it is easy to consider other objectives like wire area or power dissipation, or to add constraints to the solution. Also, wire capacitance lookup tables, or very general wire capacitance models which can capture area capacitance, fringing capacitance, coupling capacitance, etc. can be used.

Power optimal dual-V/sub dd/ buffered tree considering buffer stations and blockages

This paper presents the first in-depth study on applying dual V/sub dd/ buffers to buffer insertion and multi-sink buffered tree construction for power minimization under delay constraint. To tackle the problem of dramatic complexity increment due to simultaneous delay and power consideration and increased buffer choices, we develop a sampling-based sub-solutions (i.e. options) propagation method and a balanced search tree-based data structure for option pruning. We obtain 17/spl times/ speedup with little loss of optimality compared to the exact option propagation. Moreover, compared to buffer insertion with single V/sub dd/ buffers, dual-V/sub dd/ buffers reduce power by 23% at the minimum delay specification. In addition, compared to the delay-optimal tree using single V/sub dd/ buffers, our power-optimal buffered tree reduces power by 7% and 18% at the minimum delay specification when single V/sub dd/ and dual V/sub dd/ buffers are used respectively.

Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random L eff Variation

This paper presents extensions of the dynamic-programming (DP) framework to consider buffer insertion and wire-sizing under effects of process variation. We study the effectiveness of this approach to reduce timing impact caused by chemical-mechanical planarization (CMP)-induced systematic variation and random Leff process variation in devices. We first present a quantitative study on the impact of CMP to interconnect parasitics. We then introduce a simple extension to handle CMP effects in the buffer insertion and wire sizing problem by simultaneously considering fill insertion (SBWF). We also tackle the same problem but with random Leff process variation (vSBWF) by incorporating statistical timing into the DP framework. We develop an efficient yet accurate heuristic pruning rule to approximate the computationally expensive statistical problem. Experiments under conservative assumption on process variation show that SBWF algorithm obtains 1.6% timing improvement over the variation-unaware solution. Moreover, our statistical vSBWF algorithm results in 43.1% yield improvement on average. We also show that our approaches have polynomial time complexity with respect to the net-size. The proposed extensions on the DP framework is orthogonal to other power/area-constrained problems under the same framework, which has been extensively studied in the literature

Leveraging delay slack in flip-flop and buffer insertion for power reduction

We show that the delay slack can be distributed optimally between flip-flops to reduce power in a pipelined interconnect, and such power reduction can be achieved by simultaneous flip-flop and buffer insertion satisfying latency and delay constraints specified at sinks. We develop a dynamic programming algorithm with effective pruning rules and pseudo polynomial time complexity with respect to the decimation and the length of a net. Experiments using a cluster of interconnect in a leading industrial high-performance design show that there exists plenty of useful slack for power reduction. Without jeopardizing the delay specification, as much as 17% of power can be saved for this cluster of interconnects.

Power-optimal repeater insertion considering Vdd and Vth as design freedoms

This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and V^dd and V^th levels for a net with a delay target, and it reduces more than 50% power over a previous work which does not consider V^dd and V^th optimization. This work further presents the power saving when multiple V^dd and V^th levels are used in repeater insertion at the full-chip levelCompared to the case with single V^dd and V^th suggested by ITRS, optimized dual V^dd and dual V^th reduce overall global interconnect power by 47%, 28% and 13% for 130nm, 90nm and 65nm technology nodes, respectively, but extra V^dd or V^th levels only give marginal improvement. We also show that an optimized single V^th reduce interconnect power almost as effective as dual-V^th does, in contrast to the need of dual V^th for logic circuits

Fast dual-vdd buffering based on interconnect prediction and sampling

This paper presents fast algorithms for power-optimal interconnect synthesis based on interconnect prediction and sampling considering dual Vdd buffers. We present three pruning techniques including interconnect prediction based pruning (pre-buffer slack pruning and predictive min-delay pruning) and sampling (3D sampling), of which 3D sampling is effective but the other two improve both efficiency and accuracy of sampling. We also show that the key to runtime reduction is to reduce the number of propagated options, while the sophisticated data-structures which have good amortized complexity do not necessarily reduce runtime. We obtain an empirically linear time algorithm with less than 1% of delay and power increase but over 50x speedup compared with the most efficient algorithm for dual Vdd buffer insertion. In addition, we further enhance the power-optimal buffered tree construction by introducing routing grid reduction. We apply our speedup techniques to buffered tree construction algorithm. Experimental results show that we obtain over 100x speedup compared with the most efficient existing algorithms for dual Vdd buffered tree construction.