Kiran Gunnam

Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard

We present a new multi-rate architecture for decoding block LDPC codes in IEEE 802.11n standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. Techniques of data-forwarding and out-of-order processing are used to deal with the irregularity of the codes. The decoder has the following advantages when compared to recent state-of-the-art architectures: 55% savings in memory, reduction of routers by 50% and increase of throughput by 2times.

Vision-Based Sensor and Navigation System for Autonomous Air Refueling

Autonomous in-flight aerial refueling is an important capability for the future deployment of unmanned aerial vehicles, because they will likely be ferried in flight to overseas theaters of operation instead of being shipped unassembled in containers. A reliable sensor, capable of providing accurate relative position measurements of sufficient bandwidth, is key to such a capability. A vision-based sensor and navigation system is introduced that enables precise and reliable probe-and-drogue autonomous aerial refueling for non-micro-sized unmanned aerial vehicles. A performance robust controller is developed and integrated with the sensor system, and feasibility of the total system is demonstrated by simulated docking maneuvers with both a stationary drogue and a drogue subjected to light turbulence. An unmanned air vehicle model is used for controller design and simulation. Results indicate that the integrated sensor and controller enables precise aerial refueling, including consideration of realistic measurement errors and disturbances.

VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2times when compared to the recent state-of-the-art decoder architectures.

A vision-based DSP embedded navigation sensor

Spacecraft missions such as spacecraft docking and formation flying require high-precision relative position and attitude data. Deep space missions require the use of alternative technologies. One such technology is the vision-based navigation (VISNAV) sensor system developed at Texas A&M University. VISNAV comprises an electro-optical sensor combined with light sources or beacons. This patented sensor has an analog detector in the focal plane with a rise time of a few microseconds. Accuracies better than one part in 2000 of the field of view have been obtained. Simultaneous activation of beacons with frequency division multiplexing is given as part of the VISNAV sensor system. The synchronous demodulation process uses digital heterodyning and decimating filter banks on a low-power fixed point digital signal processor, which improves the accuracy of the sensor measurements and the reliability of the system. This paper also presents an optimal and computationally efficient six-degree-of-freedom estimation algorithm using a new measurement model based on the attitude representation of modified Rodrigues parameters.

A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes

The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data-reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requirements of the decoder when compared to the state-of-the-art LDPC decoders. The ASIC implementation of the proposed fully parallel architecture achieves throughput of 4.6 Gbps (for a maximum of 15 iterations). The chip size is 2.3 mm times 2.3 mm in 0.13 micron technology

Trellis-Based Extended Min-Sum Algorithm for Non-Binary LDPC Codes and its Hardware Structure

In this paper, we present an improvement and a new implementation of a simplified decoding algorithm for non-binary low density parity-check codes (NB-LDPC) in Galois fields GF(q). The base algorithm that we use is the Extended Min-Sum (EMS) algorithm, which has been widely studied in the recent literature, and has been shown to approach the performance of the belief propagation (BP) algorithm, with limited complexity. In our work, we propose a new way to compute modified configuration sets, using a trellis representation of incoming messages to check nodes. We call our modification of the EMS algorithm trellis-EMS (T-EMS). In the T-EMS, the algorithm operates directly on the deviation space by considering a trellis built from differential messages, which serves as a new reliability measure to sort the configurations. We show that this new trellis representation reduces the computational complexity, without any performance degradation. In addition, we show that our modifications of the algorithm allows to greatly reduce the decoding latency, by using a larger degree of hardware parallelization.

Vision Based Sensor and Navigation System for Autonomous Aerial Refueling

Autonomous in-flight aerial refueling is an important capability for the future deployment of unmanned aerial vehicles, because they will likely be ferried in flight to overseas theaters of operation instead of being shipped unassembled in containers. A reliable sensor, capable of providing accurate relative position measurements of sufficient bandwidth, is key to such a capability. A vision-based sensor and navigation system is introduced that enables precise and reliable probe-and-drogue autonomous aerial refueling for non-micro-sized unmanned aerial vehicles. A performance robust controller is developed and integrated with the sensor system, and feasibility of the total system is demonstrated by simulated docking maneuvers with both a stationary drogue and a drogue subjected to light turbulence. An unmanned air vehicle model is used for controller design and simulation. Results indicate that the integrated sensor and controller enables precise aerial refueling, including consideration of realistic measurement errors and disturbances.

Low-Power VLSI Design of LDPC Decoder Using DVFS for AWGN Channels

This paper presents a low-power LDPC decoder design for additive white Gaussian noise (AWGN) channels. The proposed decoding scheme provides constant-time decoding and thus facilitates real-time applications where guaranteed data rate is required. It analyzes each received data frame to estimate the maximum number of necessary iterations for frame convergence. The results are then used to dynamically adjust decoder frequency and switch between multiple-voltage levels; thereby energy use is minimized. It differs from recent publications on speculative LDPC decoding for block-fading channels. Our approach addresses the more difficult problem of decoding requirement prediction for data frames in AWGN channels. It is also directly applicable for fading channels. A decoder architecture utilizing offset min-sum layered decoding algorithm is presented. Up to 30% saving in decoding energy consumption is achieved with negligible coding performance degradation.

An LDPC decoding schedule for memory access reduction

Recent research efforts based on a joint code-decoder design methodology have shown that it is possible to construct structured LDPC (low density parity check) codes without any performance degradation. An interesting new data independence property between the two classes of messages viz. check to bit and bit to check, involved in decoding, is observed. This property is a result of the specific structuring of the parity check matrix. By exploiting this property, we propose an architecture in which the computation of messages is synchronized such that each class of message is consumed immediately by the computational unit for another class of message. The internal memory of the check to bit units is increased in tune with the storage requirement of the check to bit messages. The separate memories for check to bit and bit to check messages are eliminated. This approach has memory savings of 75% and reduces the overall memory accesses by 66%.

Next generation iterative LDPC solutions for magnetic recording storage

Low-density parity-check (LDPC) codes have received considerable attention as a next-generation coding technique for communication and storage channels. The developments in the hardware storage business include hard disk drives that support higher capacities and transfer rate credit to perpendicular recording. To meet the demanding error correction requirements at a lower silicon cost, most storage systems manufacturers have started adopting LDPC based error correction systems. This paper summarizes the research on low complexity LDPC decoder architecture with statistical buffer management for magnetic recoding channels that require data rates of over 5 Gbps, real time bit error rates in the order of 10-12, and quasi real time bit error rates in the order of 10-15.