Kiran S. Panesar
Intel
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Publication
Featured researches published by Kiran S. Panesar.
winter simulation conference | 1994
Samir Ranjan Das; Richard M. Fujimoto; Kiran S. Panesar; Don Allison; Maria Hybinette
The design of the Georgia Tech Time Warp (GTW, version 2.0) executive for cache-coherent shared-memory multiprocessors is described. The programmers interface is presented. Several optimizations used to efficiently realize key functions such as event list manipulation, memory and buffer management, and message passing are discussed. An efficient algorithm for computing GVT on shared-memory multiprocessors is described. Measurements of a wireless personal communication services (PCS) network simulation indicate the GTW simulator is able to sustain performance as high as 335,000 committed events per second for this application on a 42-processor KSR-2 machine.
workshop on parallel and distributed simulation | 1996
Darrin West; Kiran S. Panesar
We present an Incremental State Saving technique for which the state saving calls are inserted automatically by directly editing the application executable. This method has the advantage of being easy to use since it is fully automatic, and has good performance since it adds overhead only where state is being modified. Since the editing happens on executable code, the method is independent of the compiler, and allows third party libraries to be used. None of the previous incremental state saving methods have both of these features. We find that it is beneficial to use Automatic Incremental State Saving if less than 15% of the state is modified in each event as compared to copy state saving. This technique allows us to efficiently parallelize existing simulations, and makes Time Warp more accessible to non-Time Warp experts.
workshop on parallel and distributed simulation | 1995
Richard M. Fujimoto; Kiran S. Panesar
Mechanisms for managing message buffers in Time Warp parallel simulations executing on cache-coherent shared-memory multiprocessors are studied. Two simple buffer management strategies called the sender pool and receiver pool mechanisms are examined with respect to their efficiency, and in particular, their interaction with multiprocessor cache-coherence protocols. Measurements of implementations on a Kendall Square Research KSR-2 machine using both synthetic workloads and benchmark applications demonstrate that sender pools offer significant performance advantages over receiver pools. However, it is also observed that both schemes, especially the sender pool mechanism, are prone to severe performance degradations due to poor locality of reference in large simulations using substantial amounts of message buffer memory. A third strategy called the partitioned buffer pool approach is proposed that exploits the advantages of sender pools, but exhibits much better locality. Measurements of this approach indicate that the partitioned pool mechanism yields substantially better performance than both the sender and receiver pool schemes for large-scale, small-granularity parallel simulation applications. The central conclusions from this study are: (1) buffer management strategies play an important role in determining the overall efficiency of multiprocessor-based parallel simulators, and (2) the partitioned buffer pool organization offers significantly better performance than the sender and receiver pool schemes. These studies demonstrate that poor performance may result if proper attention is not paid to realizing an efficient buffer management mechanism.
Archive | 2010
Suresh Sugumar; Kiran S. Panesar
Archive | 2004
Michael A. Goldsmith; Kiran S. Panesar
Archive | 2006
Suresh Sugumar; Kiran S. Panesar; Narayan N. Iyer
Archive | 2006
Kiran S. Panesar
workshop on parallel and distributed simulation | 1997
Kiran S. Panesar; Richard M. Fujimoto
Archive | 2006
David A. Koufaty; John I. Garney; Ulhas Warrier; Kiran S. Panesar
Archive | 2004
Philip R. Lantz; Michael A. Goldsmith; Kiran S. Panesar