Kizheppatt Vipin

ZyCAP: Efficient Partial Reconfiguration Management on the Xilinx Zynq

New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

A high speed open source controller for FPGA Partial Reconfiguration

Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.

Architecture-Aware reconfiguration-centric floorplanning for partial reconfiguration

Partial reconfiguration (PR) has enabled the adoption of FPGAs in state of the art adaptive applications. Current PR tools require the designer to perform manual floorplanning, which requires knowledge of the physical architecture of FPGAs and an understanding of how to floorplan for optimal performance and area. This has lead to PR remaining a specialist skill and made it less attractive to high level system designers. In this paper we introduce a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs. It takes into account overheads generated due to PR as well as the architecture of the latest FPGAs. This results in a floorplan that is efficient for PR systems, where reconfiguration time and area should be minimised.

Virtualized FPGA Accelerators for Efficient Cloud Computing

Hardware accelerators implement custom architectures to significantly speed up computations in a wide range of domains. As performance scaling in server-class CPUs slows, we propose the integration of hardware accelerators in the cloud as a way to maintain a positive performance trend. Field programmable gate arrays (FPGAs) represent the ideal way to integrate accelerators in the cloud, since they can be reprogrammed as needs change and allow multiple accelerators to share optimised communication infrastructure. We discuss a framework that integrates reconfigurable accelerators in a standard server with virtualised resource management and communication. We then present a case study that quantifies the efficiency benefits and break-even point for integrating FPGAs in the cloud.

DyRACT: A partial reconfiguration enabled accelerator and test platform

Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. The interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.

Automated Partitioning for Partial Reconfiguration Design of Adaptive Systems

Adaptive systems have the ability to respond to environmental conditions by modifying their processing at runtime. This can be implemented by using partial reconfiguration (PR) on FPGAs. However, designing such systems requires specialist architecture knowledge and an understanding of the mechanics of reconfiguration, as the design process is completely manual. One design choice that must be made, which impacts system efficiency significantly, is how to group reconfigurable modules and assign them to reconfigurable regions on the FPGA. In this paper, we present an approach, based on graph clustering, that finds a partitioning that minimises reconfiguration time, given an application description and target FPGA. The resulting allocation respects all the constraints set by the official tool flow while raising the level of design abstraction, allowing non-expert designers to leverage this capability of FPGAs.

System-level FPGA device driver with high-level synthesis support

We can exploit the standardization of communication abstractions provided by modern high-level synthesis tools like Vivado HLS, Bluespec and SCORE to provide stable system interfaces between the host and PCIe-based FPGA accelerator platforms. At a high level, our FPGA driver attempts to provide CUDA-like driver behavior, and more, to FPGA programmers. On the FPGA fabric, we develop an AXI-compliant, lightweight interface switch coupled to multiple physical interfaces (PCIe, Ethernet, DRAM) to provide programmable, portable routing capability between the host and user logic on the FPGA. On the host, we adapt the RIFFA 1.0 driver to provide enhanced communication APIs along with bitstream configuration capability allowing low-latency, high-throughput communication and safe, reliable programming of user logic on the FPGA. Our driver only consumes 21% BRAMs and 14% logic overhead on a Xilinx ML605 platform or 9% BRAMs and 8% logic overhead on a Xilinx V707 board. We are able to sustain DMA transfer throughput (to DRAM) of 1.47GB/s (74% peak) of the PCIe (x4 Gen2) bandwidth, 120.2MB/s (96%) of the Ethernet (1G) bandwidth and 5.93GB/s (92.5%) of DRAM bandwidth.

An approach for redundancy in FlexRay networks using FPGA partial reconfiguration

Safety-critical in-vehicle electronic control units (ECUs) demand high levels of determinism and isolation, since they directly influence vehicle behaviour and passenger safety. As modern vehicles incorporate more complex computational systems, ensuring the safety of critical systems becomes paramount. One-to-one redundant units have been previously proposed as measures for evolving critical functions like x-by-wire. However, these may not be viable solutions for power-constrained systems like next generation electric vehicles. Reconfigurable architectures offer alternative approaches to implementing reliable safety critical systems using more efficient hardware. In this paper, we present an approach for implementing redundancy in safety-critical in-car systems, that uses FPGA partial reconfiguration and a customised bus controller to offer fast recovery from faults. Results show that such an integrated design is better than alternatives that use discrete bus interface modules.

Dynamic Cognitive Radios on the Xilinx Zynq Hybrid FPGA

Cognitive radios require an intelligent MAC layer coupled with a flexible PHY layer. Most implementations use software defined radio platforms where the MAC and PHY are both implemented in software, but this can result in long processing latency, and makes advanced baseband processing unattainable. While FPGA based SDR platforms do exist, they are difficult to use, requiring significant engineering expertise, and adding dynamic behaviour is even more difficult. Modern hybrid FPGAs tightly couple an FPGA fabric with a capable embedded processor, allowing the baseband to be implemented in hardware, and the MAC in software. We demonstrate a platform that enables radio designers to build dynamic cognitive radios using the Xilinx Zynq with partial reconfiguration, enabling truly dynamic, low-power, high-performance cognitive radios with abstracted software control.

Efficient region allocation for adaptive partial reconfiguration

While partial reconfiguration on FPGAs has attracted significant research interest in recent years, designing systems that leverage it remains a specialist skill. Systems with a large number of reconfigurable modules can be challenging to design. Deciding on how many reconfigurable regions to use is not always straightforward, yet this choice impacts area efficiency and configuration latency. Current FPGA partial reconfiguration tool flows require the designer to have detailed knowledge of the physical architecture of the FPGA. It is the responsibility of the designer to decide on the location and size of regions. In this paper we introduce a formulation for determining the tradeoff between the number of reconfigurable regions, the allocation of modules to regions, and the reconfiguration overhead, represented by area and reconfiguration time. Throughout the investigation, we consider the heterogeneous nature of modern FPGAs as well as limitations imposed by current tools. We then show that adopting an optimal allocation can result in both area savings and a reduction in reconfiguration time over a standard approach to allocation.