Klaas Bult

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A technique that combines the high-frequency behavior of a single-stage op amp with the high DC gain of a multistage design is presented. This technique is based on the concept that a very high DC gain can be achieved in combination with any unity-gain frequency achievable by a (folded-) cascode design. Bode-plot measurements for an op amp realized in a 1.6- mu m process show a DC gain of 90 dB and a unity-gain frequency of 116 MHz (16-pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding to a closed-loop bandwidth of 18 MHz (35-pF load) and a settling accuracy better than 0.03%. This technique does not cause any loss in output voltage swing. At a supply voltage of 5.0 V an output swing of about 4.2 V is achieved without loss in DC gain. The above advantages are achieved with a 30% increase in chip area and a 15% increase in power consumption. >

An inherently linear and compact MOST-only current division technique

A technique is presented that uses the same MOS transistors for both division and switching functions, eliminating resistors or capacitors. Although an MOS-transistor exhibits a nonlinear relation between the current and voltage (even in the linear region), it is shown that the current division is inherently linear. The most important measurement results are shown. The dynamic range in the audio-band (0-20 kHz) is 103 dB with respect to a maximum input signal of 1 V/sub rms/. At 1 V/sub rms/, THD is below -80 dB over the audio band and below -85 dB under 3 kHz. As the unity-gain frequency of the opamps is 4.5 MHz, the bandwidth of the circuit is limited to 1.5 MHz. Attenuation accuracy is better than 0.15 dB up to -48 dB and better than 0.4 dB over the entire attenuation range. >

The CMOS gain-boosting technique

The gain-boosting technique improves accuracy of cascoded CMOS circuits without any speed penalty. This is achieved by increasing the effect of the cascode transistor by means of an additional gain-stage, thus increasing the output impedance of the subcircuit. Used in opamp design, this technique allows the combination of the high-frequency behavior of a single-stage opamp with the high DC-gain of a multistage design. Bode-plot measurements show a DC-gain of 90 dB and a unity-gain frequency of 116 MHz (16 pF load). Settling measurements with a feedback factor of 1/3 show a fast single-pole settling behavior corresponding with a closed-loop bandwidth of 18 MHz (35 pF load) and a settling accuracy better than 0.03 percent. A more general use of this technique is presented in the form of a transistor-like building block: the Super-MOST. This compound circuit behaves as a normal MOS-transistor but has an intrinsic gain gm.ro of more than 90 dB. The building block is self-biasing and therefore very easy to design with. An opamp consisting of only 8 Super-MOSTs and 4 normal MOSTs has been measured showing results equivalent to the design mentioned above.

A fast-settling CMOS op amp with 90 dB DC-gain and 116 MHz unity-gain frequency

An op amp that exhibits single-pole settling behavior using an auxiliary amplifier that boosts gain without degrading settling time is described. The technique for increasing the DC gain is based on increasing cascoding by adding an additional gain stage. In this way the output impedance present at a node is increased by the gain of the additional gain stage.<<ETX>>