Klaus Hummler

Optimized testing of on-chip error correction circuit

METHOD FOR ACHIEVING HIGH SELF-ALIGNING VERTICAL GATE STUDS RELATIVE TO THE SUPPORT ISOLATION LEVEL

Repair of semiconductor memory device via external command

NONVOLATILE MEMORY CELL

Isolating a vertical gate contact structure

Memory having parity error correction

Memory having parity generation circuit

Data inversion device and method

Spacer assisted trench top isolation for vertical DRAM's

SEMICONDUCTOR DEVICE WITH DEEP TRENCH ISOLATION AND METHOD OF MANUFACTURING SAME