Klaus Waldschmidt

Repartitioning and technology mapping of electronic hybrid systems

The systematic top-down design of mixed-signal systems requires an abstract specification of the intended functions. However, hybrid systems are systems whose parts are specified using different time models. Specifications of hybrid systems are not purely functional as they also contain structural information. The structural information is introduced by partitioning the specification into blocks with a homogeneous time model. This often leads to inefficient implementations. In order to overcome this problem, a homogeneous representation for behavior of hybrid systems-KIR-is introduced. This representation makes it possible to represent behavior in all time models in a common way so that the separation in different modeling styles is no longer necessary. Rules for re-writing the KIR-graph are given which permit the description of the same behaviour in another time model.

KIR—a graph-based model for description of mixed analog/digital systems

Systems can be described in different time models and on various levels of abstraction. We can distinguish between models in discrete-event, discrete and continuous time. Graph-based formal models allow us to use either discrete event/discrete time models or continuous time models. The combined use of all three time models in one system is the main problem when modeling mixed analog/digital systems. In this paper a graph-based model is presented that supports the use of all three time models in different parts of a graph. This allows digital, discrete-time systems to be modeled together with their analog, physical environment.

Reliability-Aware Power Management of Multi-Core Processors

Long-term reliability of processors is experiencing growing attention since decreasing feature sizes and increasing power consumption have a negative influence on the lifespan. The reliability can also be influenced by Dynamic Power Management (DPM), since it affects the processor’s temperature.

Mixed-Signal Extensions for SystemC

SystemC supports a wide range of Models of Computation (MoC) and is very well suited for the design and refinement of HW/SW-systems from functional downto register transfer level. However, for a broad range of applications the digital parts and algorithms interact with analog parts and the continuous-time environment. Due to the complexity of this interactions and the dominance of the analog parts in respect to the system behavior, is it essential to consider the analog parts within the design process of an Analog and Mixed Signal System. Therefore simulation performance is very crucial - especially for the analog parts. Thus different and specialized analog simulators must be introduced to permit the use of the most efficient solver for the considered application and level of abstraction. In this paper we describe possible areas of application and formulate requirements for analog and mixed-signal extensions for SystemC

KANDIS—a tool for construction of mixed analog/digital systems

The synthesis of electronic circuits on system level offers the possibility to find better locations of the A/D interfaces and to determine parameters like clock rates and bit widths. KANDIS, a tool for (K)construction of mixed ANalog/DIgital Systems, uses a structure-oriented expert system for these tasks. The main idea is the successive construction on functional and algorithmic blocks with different kinds of tools and the permanent exchange of resource limitations with constraint propagation.

SDVM^R: A Scalable Firmware for FPGA-Based Multi-core Systems-on-Chip

FPGAs offering dynamic reconfiguration make new approaches for parallel computing possible: Changing the number and type of processing elements at runtime offers an important step to adaptive behaviour of systems-on-chip. In this paper the implementation of a virtualization layer between applications and FPGA-hardware is described. This virtualization allows a transparent runtime-reconfiguration of the underlying hardware for adaption to changing system environments. The application does not see the underlying, even heterogeneous hardware. Many of the requirements for such a virtualization layer are met by the SDVM, the scalable dataflow-driven virtual machine. This paper describes some aspects of the reimplementation and adaptation of the SDVM to modern platform FPGAs. It describes different possible approaches to use the available resources and discusses several technical questions regarding the implementation.

The SDVM - an approach for future adaptive computer clusters

The self distributing virtual machine (SDVM) is a parallel computing machine which consists of a cluster of customary computers. The participating machines may have different computing speed or actually different operating systems, and any network topology between them is supported. As the SDVM supports dynamic entry and exit at runtime, the cluster may even grow or shrink without disturbing the program flow. Among other features, the SDVM features decentralized scheduling and automatic distribution of data and program code throughout the cluster. Therefore machines need no prerequisites apart from the SDVM daemon itself to join the cluster. The concept of the SDVM is implemented for the field of computer clusters (extensible to grid computing like the Internet), but it can be designed for multi-processor-systems or systems-on-chip (SoC) as well. This paper presents the properties and the structure of the SDVM.

A methodology for system-level synthesis of mixed-signal applications

This paper gives an overview of a methodology for the design of mixed-signal systems. The methods support the user in defining important system parameters such as sampling frequencies, bit widths, or the type of applicable analog-to-digital converters. This is done by a knowledge-based system, which calculates estimations for the resulting system properties. The methodology starts with an abstract specification of the intended behavior, which is mapped onto a block diagram. The block diagram can then be evaluated by knowledge-based methods and by simulation. The methods have been implemented as a prototypical design tool, which has been used for the design of several case studies.

Combining static partitioning with dynamic distribution of threads

This paper presents a hybrid approach to automatic parallelization of computer programs which combines static extraction of threads (tasks) with dynamic scheduling for parallel and distributed execution. Fine-grain scheduling decisions are made at compile time, and coarse-grain scheduling decisions are made at run time. The approach consists of two components: compiler technology which performs the static analysis (thread extraction), and an architecture which takes over the responsibility for scheduling and distributing the threads. Each processor is augmented with a broker, whose responsibility it is to shop for tasks for the processor to perform. This approach aims to provide an adaptive run-time distribution of computation for irregular problems such as the simulation of embedded systems. Finally, this approach is general enough to allow the seamless incorporation of heterogeneous hardware, in particular including dynamically reconfigurable hardware, e.g. FPGAs.

Adaptive system architectures

Summary form only given. Embedded systems, ubiquitous computing, and networked architectures are research areas in computer science where the features of organic computing become increasingly essential. Such features, like self organization and self configuration need to be combined with the still increasing requirement for computing performance. Adaptive computing systems are a promising completion to classical computer architectures. Adaptive computing systems (ACS) offers the opportunity to adapt the whole architecture or parts of the architecture to the changing needs of applications or changing environments. Reconfigurable logic (RL) can itself contain mono- or multiprocessors or it can be a component in such systems or computer clusters. All levels of parallelism can be combined with all levels of reconfigurability. Configuration and concurrency offer a huge design space to be explored. They become tightly correlated issues in modem adaptive computer architectures. Different grains of configurability bring the flexibility into architectures. This flexibility is necessary to achieve a better exploitation of parallelism in algorithms. Architectures can thus be adapted to all the needs of problems or algorithms to turn the inherent or explicit parallelism into efficiency. We address some of these aspects and present some ideas for modelling and classifying adaptive computing systems (ACS) on different levels of granularity.