Klaus Y. J. Hsu

An Integrated Low-Noise Sensing Circuit With Efficient Bias Stabilization for CMOS MEMS Capacitive Accelerometers

A sensing circuit in 0.35 μm CMOS technology for CMOS MEMS capacitive accelerometers has been designed in this work with emphasis on managing noise, sensor offset, and the dc bias at input terminals. The issue of dc bias is particularly addressed and an efficient method is proposed. An example of integrating surface micromachined sensors and the designed sensing circuits on the same chip is demonstrated. Experimental results showed that the proposed circuit led to good noise performance, the random offset in the sensors was efficiently compensated, and the input dc bias voltage was well maintained. The sensitivity of the accelerometer is 457 mV/g. The output noise floor is 54 μg/√Hz, which corresponds to an effective capacitance noise floor of 0.0162 aF/√Hz. The total area of the dual-axis surface micromachined accelerometer chip is 5.66 mm2 and the current consumption is 1.56 mA under a 3.3 V voltage supply.

High-Responsivity Photodetector in Standard SiGe BiCMOS Technology

For high-speed optoelectronic applications such as fiber-optic data communication systems, photodetectors (PDs) with high responsivity in Si-related processes are required. In this letter, a result of the effort along this line is reported. A novel device named phototransistor PD (PTPD) was realized in a commercial 0.35-mum SiGe BiCMOS technology. The device combines a surface PD (SPD) and a conventional SiGe heterojunction PT (HPT). It was shown that the SPD enhanced light absorption and the PTPD showed significant performance improvement over HPT. Responsivities of 5.2 A/W for an 850-nm light and 9.5 A/W for a 670-nm light were achieved in the PTPD, with floating base and SPD terminals.

Fundamental studies of p-type doping of CdTe

Abstract This paper reviews recent developments of p-type doping in CdTe, in which hole concentrations of 5 × 1019cm−3 have been obtained with phosphorus ion implantation and pulsed electron beam annealing. The implant and damage profiles, and the atom redistribution after the annealing were calculated to explain the experimental results. Defect models were proposed to further illustrate the doping mechanisms. The creation and the annihilation of the phosphorus interstitials were explained by analyzing the electronic structure of the phosphorus interstitial following a molecular orbital approach and density functional theory. All these results confirmed the importance of the melting effect of pulsed electron beam (PEB) annealing in obtaining the highest doping efficiencies in II–VI compounds.

Reliability study of sub-micron titanium silicide contacts

Abstract Kelvin bridge type contact resistance test structures were fabricated for studying the behavior of p-type titanium silicide contacts of sub-micron dimensions. The shallow junctions were formed by using the implant through metal (ITM) technique. SIMS profiles showed that the boron concentration at the silicide-Si interface was about 2 × 1020 cm−3. The resulted specific contact resistivity was in the range of (3–6) × 10 −7 Ω· cm 2 . For the contacts whose smallest size is 0.5 × 0.5 μm2, the contact resistance still increased linearly with the inverse of contact area. Electrical stress test revealed that the sub-micron contacts exhibited degradation phenomena even though a titanium tungsten layer was deposited prior to depositing aluminum contact pads. In some cases, the degradation rate was found to be dependent on the polarity of stressing current. This study indicates that the reliability of sub-micron contacts needs to be seriously considered.

Characterization of Ultrathin Dielectrics Grown by Microwave Afterglow Oxygen and N2O Plasma.

Ultrathin dielectrics, oxides and oxynitrides were grown using microwave afterglow oxygen and N 2 O plasma at low temperature. N 2 O plasma annealing and pretreatment improved the breakdown properties of O 2 plasma oxides. From secondary ion mass spectroscopy (SIMS) analysis, nitrogen was found to be incorporated into oxides effectively by this low-temperature method. Nitrogen content was highest at the oxide surface and decreased toward the oxide/Si interface. This indicates a nitridation mechanism different from the conventional N 2 O gas annealing or oxidation processes. The relationships among interface state densities, tunneling current and nitrogen profiles were also investigated by C-V and I-V measurements

Design and Properties of Phototransistor Photodetector in Standard 0.35-

In this paper, without altering any step of the commercial 0.35-mum SiGe BiCMOS process, a novel photodetector named phototransistor photodetector (PTPD) has been realized and demonstrated. The PTPD shows high photoresponsivity and its structure relaxes the tradeoff between sensitivity and speed. Responsivities of 9.5 A/W for 670 nm light and of 5.2 A/W for 850 nm light were achieved. The operation details of the PTPD are introduced in this paper. The device can be readily integrated with other on-chip circuits to form a high-performance optoelectronic IC. The low cost, the high performance, and the flexibility in optical-electrical design allow the SiGe PTPD to be used in many demanding applications.

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Structure curling induces thermal instability into CMOS MEMS capacitive sensors. The charging effect during reactive ion etching damages the existing on-chip MOS transistors and drastically reduces the yield rate of chips. This paper presents a novel post-CMOS process that solves the problems and leads to CMOS MEMS capacitive sensors with high sensitivity and thermal stability. The novel process was demonstrated with a capacitive accelerometer in 0.35 µm CMOS technology. The accelerometer contains a thermally stable MEMS sensor and an on-chip CMOS sensing circuit with a chopper stabilization scheme. The temperature stabilization was achieved by forming a thick single-crystal silicon (SCS) layer at the bottom of the multi-layer MEMS structure. No leakage current due to charge damage was ever observed in the sample chips. The proposed process also led to minimal undercut of the SCS layer after MEMS structure release. The sensitivity of the accelerometer is 595 mV g−1, and the overall noise floor is 50 µg Hz−1/2 which corresponds to an effective capacitance noise floor of 0.024 aF Hz−1/2. The zero-g temperature coefficient of the accelerometer output voltage is only 1 mV °C−1 in the temperature range from 0 to 70 °C, which corresponds to an effective acceleration variation rate of 1.68 mg °C−1.

m SiGe BiCMOS Technology

Two-dimensional porous silicon structures were modeled as two-dimensional directional site percolated networks (2D-DSPNs). In the present work, the 2D-DSPNs were modeled as resistive networks, and the electrical conductance values were numerically calculated. The effects of porosity and geometrical connection on the electrical conduction behavior were isolated and identified. It was shown that the geometrical connection of 2D-DSPNs makes the conduction behavior distinctly different from that in traditional random networks. A geometry anisotropic random walk model was developed to microscopically understand the macroscopic conduction behavior of 2D-DSPNs.

A new process for CMOS MEMS capacitive sensors with high sensitivity and thermal stability

Wireless time signal broadcast system is an essential platform for the operation of radio watches. It is also a good system for broadcasting other civil information such as disaster warning. To obtain wide coverage area, the carrier frequency is usually as low as tens of kHz. When designing receiver front-end ICs in this low-frequency range, noise consideration is critical. In this paper, the design of a low-power, low-noise receiver front-end IC in 0.35 μm SiGe BiCMOS technology for low frequency time signal broadcast system is reported. The front-end IC tolerates wide input dynamic range of 106 dB and has high sensitivity. With 3.3 V supply voltage, the IC only consumes 0.343 mW when working. Stand-by mode has been implemented to save even more energy. The chip area is only 1300 μm × 908 μm, including ESD protection and bonding pads.

Electrical conductance simulation of two-dimensional directional site percolated networks for porous silicon structures

Abstract The structure of porous silicon (PS) was simulated by a two-dimensional site-percolated network model. In this model, both porosity and geometrical morphology were independently controlled. The conductivity of the generated PS structures were numerically simulated, and the effects of porosity and geometrical connection of PS on the conduction behavior of percolated Si network were isolated and identified. It was shown that the geometrical connection of PS causes its conduction behavior to become distinctly different from that in a random network.