Kohichi Nakayama

OPC to reduce variability of transistor properties

Scaling toward 65 nm and beyond, process variations are increased and influences both functional yield and parametric yield. The process variations consist of systematic components and random components. Systematic variations are caused by predictable design and process procedures, therefore systematic variations should be removed from process corner model for LSI design. With the effect of scaling, print images on a wafer shows complicated distortion. The method of calculating distorted transistor properties without slicing into individual rectangular transistors has been previously proposed. Using this calculation method, transistor properties with distortion are able to be calculated, reduction of transistor property variations is expected. Transistor property variations caused by layout dependence could be reduced by using OPC with SPICE for each transistor, however, the calculation time of gate length retarget with SPICE is not realistic. Therefore we have investigated approximation for transistor properties using statistics of gate length distribution and layout parameters, and found that parameter fitting by average and &sgr; of gate length distribution of each transistor is useful. According to the results of application to standard cell libraries using OPC with transistor property estimation, we have achieved that our new OPC reduces threshold voltage and drive current variations greatly without increasing throughput. It is difficult to suppress variation about all properties without area penalty, however, property priority required for each transistor is different. Therefore performance improvement of the whole circuit and chip is possible by the argument of priority between manufacturing engineer and circuit designer or using design intents.

Optimization of layout design and OPC by using estimation of transistor properties

At deep sub-wavelength nodes, it is difficult to transfer accurate mask pattern onto the wafer. However, actual gate pattern is distorted, and timing analysis tools calculates circuit performance on the assumption that the same gate length exists throughout the whole gate width. We calculated the property of the original 2 dimensional distorted transistor by using distribution of gate length. Firstly, in order to evaluate the accuracy of this approach, we have compared them with experimental results that may influence the 65 nm-node design rule. In the conventional method using a rectangular model, results of transistor properties are different from the experimental values, however, results of this approach can reproduce the experimental results. Secondly, this approach is applied to optimization of layout design and OPC. In order to investigate the influence of circuit performance on a layout design and OPC, we calculated the properties (drive current; Ion and leakage current; Ioff) of each transistor contained in standard cell library which is most referred to in a system LSI. We have investigated 2 layouts and 8 OPCs. According to these results, we find out that optimal OPC differs according to the prioritization of Ion and Ioff, whether it is an N-channel or P-channel, and also by layout. Furthermore relaxation of layout decreases variability of Ion caused by defocus. Moreover, since the influence of pattern distortion can be expressed by circuit term such as Ion and Ioff in addition to conventional process terms, it becomes easier for designers to understand manufacturing issues.

Structure and data processing for PEL mask compatible with image placement accuracy in the 65-nm node and beyond

Image placement (IP) error of a 1x stencil mask is a concern for proximity electron beam lithography (PEL) when considering its application in the 65 and 45-nm nodes. According to our preliminary overlay budget for the 65-nm node, the global IP over the mask and the local IP within each membrane should be kept less than 10 and 7 nm, respectively to fulfill the total overlay accuracy of 23 nm. In this paper, we demonstrate the mask structure and the data processing method that enables the mask to be fully compatible with the local IP requirement in those technology nodes.

Complementary splitting with stress emulation for stencil masks

The practical methods for splitting line-and-space (LS) patterns and large rectangles into two complementary portions have been developed for the fabrication of stencil masks. The critical length for LS patterns can be determined from the finite-element modeling of the patterns under the external force acting up them in the wet cleaning of the mask. The optimal way of placing the split portions over the mask has also been demonstrated. On the other hand, a large pattern should be split in a step larger than half the shorter side of the figure. Since the methods are based on the simple and fast modeling, the flexible criteria as a function of design rule can be set in the splitting algorithm.