Koichi Kuzume

FPGA-based lifting wavelet processor for real-time signal detection

This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. Since our detection algorithm is very simple because of short filter length in the IHLWT, the VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders. Therefore, it can realize the high-speed detection of target signals by constructing a pipeline architecture. The VLSI is designed using hardware description language (HDL) and is simulated on the FPGA in practice. The completed prototype is tested through software-generated signals and utility-sampled signals, in which test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly. From the results, it is confirmed that the proposed processor can execute target signal detection from the measured ECG signals in real time.

Wavelet-based personal identification

This work presents a personal identification system based on the learning of the lifting dyadic wavelet filters. Our system consists of face learning, detection, and identification processes. In the learning process, free parameters in the lifting filters are determined so as to capture a facial part. Our face detection method is performed by applying the learned filters to each of the video frames. A person whose face is detected in a maximum number of frames is identified as a target person. In simulation, it is shown that our personal identification algorithm is fast and accurate.

Design of a lifting wavelet processor for one dimensional signal

This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using hardware description language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.