Koji Aoyama

5.4 GOPS linear array architecture DSP for video-format conversion

A programmable DSP with linear-array architecture for real-time video processing, including video format conversion, has 4320 SIMD processor elements, has a peak processing rate of 5.4 GOPS, and can be applied to HDTV signals with its 75 MHz peak I/O clock rate. Sufficient programmability is provided to execute video-format conversion, such as image-size conversion (ISC) and Y/C separation, and picture-quality improvement, such as noise reduction and image enhancement.

Video DSP architecture and its application design methodology for sampling rate conversion

This paper describes the special architecture of the linear array DSP and design methodology for the application to convert sampling rate of the video signals. This methodology allows us to develop a detailed DSP application code for a given sampling conversion rate. Compared to the ASIC implementation of sampling rate conversion, the required time for implementation is drastically reduced. An example of conversion from HDTV to SDTV (wide) is given.

High quality multi-scan converter for XGA-LCD projector by video DSP

This paper presents a multi-scan converter for the XGA-LCD projector using video DSP that an handle 140 (70/spl times/2) MHz peak I/O signals. Applying video DSP, the proposed system realizes high quality conversion and multi-functions for various formats. It also remarkably reduces the development term and manpower.