Koji Hosono

Advanced process control of mask dry-etching using RF sensor

Advanced process control (APC) of photomask dry-etching has been studied for strict mean control of both CD and phase angle of phase shift masks (PSMs). Equations to correlate process information with actual etching results have been developed for this purpose. It is showed that plasma reactance measured with RF sensor has noticeable correlation with Cr etching bias, which is affected by Cr load and condition of etching chamber. Simulation of etching bias based on plasma reactance shows the good agreement with the trend of actual etching results. Expectation of process capability index (Cpk) for mean-to-target (MTT) within 5.2nm is about 1.27, corresponding to CD yield more than 99.9%. In case of MoSi based PSMs, monitoring the sensor outputs is also useful to simulate the etching rate of phase shifter. One simple relationship can be also derived as the case of Cr etching bias. Expected phase error is within 1.5degree in almost cases. In actual photomask fabrication, maintenance of the equation for APC is a critical issue to guarantee the high process yield for a long period. It is showed that trend of the plasma reactance gives the meaningful information effective in automatic maintenance of the equations. As a conclusion, it is proved that our APC method is one of the answers to give the highest MTT yield for both CD and phase angle.

CD measurement point extraction from local dense patterns

Precision control of critical dimensions (CD) in modern photomask manufacturing is conventionally accomplished by measuring of CD check patterns allocated inside photomask area. Recently, due to use of immersion and High-NA processes for ArF scanners surface of photomask is subjected to higher energy exposure. Such high energy exposure not only increases the loading effect and the flare but also brings about additional issues such as Cr migration and degradation of MoSi film quality due to its surface oxidation which become a new source of CD deviation. Such phenomenon influence both local pattern shape and its dependence on pattern density and global pattern density and arrangement. To achieve good control of CD in such global environment it is required to measure patterns in the chip device area equivalent to CD check patterns allocated on that chip. However, it is extremely difficult to accurately extract coordinates of patterns for CD measurements inside large device of the chip. We have developed a system in which firstly, using design rule check (DRC) method we extract from the chip device area simple line and space (L/S) patterns similar to CD check patterns and secondly, after bitmap transformation of the extraction result use a convolution operation approach to determine the patterns to measure. We confirmed that our method enables selection of CD measurement points with good reproducibility and stability. Next, we report on details of our method to extract CD measurement points and demonstrate its usefulness due to its excellent reproducibility and stability.

Global and local factors of on-chip variation of gate length

For accurate analysis of circuit performance, an understanding on-chip gate length variation is required. Non-systematic OCLV was measured by SEM and the results were analyzed after being divided into local and global factors. Simple empirical models of global and local variations were proposed, and fitting was done. In the fitting, measured mask variation was used, and on-chip variation of focus, dose, and LWR were fitting parameters. The fit of our model was very consistent with experimental result. Prediction of global and local variation using lithographic characters of patterns, such as EL, DOF, and MEEF, was enabled.