Kong Jie

Application of the DRS4 chip for GHz waveform digitizing circuits

At present, fast waveform digitizing circuit is more and more employed in modern physics experiments for processing the signals from an array detector. A new fast waveform sampling digitizing circuit developed by us is presented in this paper. Different with the traditional waveform digitizing circuit constructed with analog to digital converter(ADC) or time to digital converter(TDC), it is developed based on domino ring sampler(DRS), a switched capacitor array(SCA) chip. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). The circuit has advantages of high resolution, low cost, low power dissipation, high channel density and small size. The quite satisfactory results are acquired by the preliminary performance test of this circuit board. Eight channels can be provided by one board, which has a 1-volt input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50ps. The several boards can be cascaded to construct a multi-board system. The good performances make the circuit board to be used not only for physics experiments, but also for other applications.A new fast waveform sampling digitizing circuit based on the domino ring sampler (DRS), a switched capacitor array (SCA) chip, is presented in this paper, which is different from the traditional waveform digitizing circuit constructed with an analog to digital converter (ADC) or time to digital converter. A DRS4 chip is used as a core device in our circuit, which has a fast sampling rate up to five gigabit samples per second (GSPS). Quite satisfactory results are acquired by the preliminary performance test for this circuit board. Eight channels can be provided by one board, which has a 1 V input dynamic range for each channel. The circuit linearity is better than 0.1%, the noise is less than 0.5 mV (root mean square, RMS), and its time resolution is about 50 ps. Several boards can be cascaded to construct a multi-board system. The advantages of high resolution, low cost, low power dissipation, high channel density and small size make the circuit board useful not only for physics experiments, but also for other applications.

Development of front-end readout electronics for silicon strip detectors

A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

Trigger design for a gamma ray detector of HIRFL-ETF

The Gamma Ray Array Detector (GRAD) is one subsystem of HIRFL-ETF (the External Target Facility (ETF) of the Heavy Ion Research Facility in Lanzhou (HIRFL)). It is capable of measuring the energy of gamma-rays with 1024 CsI scintillators in in-beam nuclear experiments. The GRAD trigger should select the valid events and reject the data from the scintillators which are not hit by the gamma-ray. The GRAD trigger has been developed based on the Field Programmable Gate Array (FPGAs) and PXI interface. It makes prompt trigger decisions to select valid events by processing the hit signals from the 1024 CsI scintillators. According to the physical requirements, the GRAD trigger module supplies 12-bit trigger information for the global trigger system of ETF and supplies a trigger signal for data acquisition (DAQ) system of GRAD. In addition, the GRAD trigger generates trigger data that are packed and transmitted to the host computer via PXI bus to be saved for off-line analysis. The trigger processing is implemented in the front-end electronics of GRAD and one FPGA of the GRAD trigger module. The logic of PXI transmission and reconfiguration is implemented in another FPGA of the GRAD trigger module. During the gamma-ray experiments, the GRAD trigger performs reliably and efficiently. The function of GRAD trigger is capable of satisfying the physical requirements.

A TOF-PET prototype with position sensitive PMT readout

A prototype of time-of-flight positron emission computed tomography (TOF-PET) has been developed for acquiring the coincident detection of 511 keV γ-rays produced from positron annihilation. It consists of two 80.5 mm×80.5 mm LYSO scintillator arrays (composed of 35 ×35 pixel finger crystals) with the position sensitive photomultiplier tubes R2487 as the readout. Each array is composed of 2 mm ×2 mm×15 mm finger crystals and the average pixel pitch is 2.30 mm. The measured results indicate that the TOF information has the potential to significantly enhance the image quality by improving the noise variance in the image reconstruction. The best spatial resolution (FWHM) of the prototype for the pairs of 511 keV γ-rays is 1.98 mm and 2.16 mm in the x and y directions, respectively, which are smaller than the average pixel pitch of 2.30 mm.