Kosuke Shiba

A prototype of a dynamically reconfigurable processor based off-loading engine for accelerating the shortest path calculation with GNU zebra

A hardware off-loading engine to speed up the shortest path calculation in OSPF (open shortest path first) has been developed. The developed system is co-designed with both hardware and software to optimize an architecture of a router for highly functional traffic engineering (TE). To speed up the shortest path calculation, we employ a dynamically reconfigurable processor, IPFlex DAPDNA-2, as a hardware off-loader, and newly structured a novel high-speed parallel shortest path algorithm, called MPSA (Multi-route Parallel Search Algorithm). The proposed algorithm consists of simple processing, in which multiple paths are simultaneously searched by multiple processor element (PE) of DAPDNA-2. Therefore, it reduces the execution time of shortest path calculation to 2.8% compared with the popular shortest path algorithm, Dijkstrapsilas algorithm. Our prototype works together with a famous software-based router, GNU Zebra, on commodity Linux PC. The proposed architecture and prototype system can be applied to future network sophisticated TE.

Fast Optimal Replica Placement with Exhaustive Search Using Dynamically Reconfigurable Processor

This paper proposes a new replica placement algorithm that expands the exhaustive search limit with reasonable calculation time. It combines a new type of parallel data-flow processor with an architecture tuned for fast calculation. The replica placement problem is to find a replica-server set satisfying service constraints in a content delivery network (CDN). It is derived from the set cover problem which is known to be NP-hard. It is impractical to use exhaustive search to obtain optimal replica placement in large-scale networks, because calculation time increases with the number of combinations. To reduce calculation time, heuristic algorithms have been proposed, but it is known that no heuristic algorithm is assured of finding the optimal solution. The proposed algorithm suits parallel processing and pipeline execution and is implemented on DAPDNA-2, a dynamically reconfigurable processor. Experiments show that the proposed algorithm expands the exhaustive search limit by the factor of 18.8 compared to the conventional algorithm search limit running on a Neumann-type processor.

Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.