Kouichi Suzuki

Study of hot spot detection using neural networks judgment

We investigated the possibility of hotspot detection after lithography simulation by using Neural Networks (NN). We applied the image recognition technique by the NN for hotspot detection and confirmed the possibility by its recognition rate of the device pattern defects after NN learning. Various test patterns were prepared for NN learning and we investigated the convergence and the learning time of the NN. The compositions of the input and the hidden-layers of the NN do not have so much influence on the convergence of NN, but the initial parameter values of weight setting have predominant effect on the convergence of the NN. There are correlations among the learning time of the NN, the number of input samples and the number of hidden-layers, so a certain consideration is required for NN design. The hotspot recognition rate ranged from 90% to 42%, depending pattern type and learning sample number. Increasing learning sample number improves the recognition rate. But learning all type patterns leads to 55% recognition, so learning single type pattern leads to better recognition rate.

A 54000-gate ECL array with substrate power supply

In microprocessor and system LSIs having several tens of thousands of gates, performance is determined by interconnection delay rather than by intrinsic gate delay because of limitations on total power consumption. This difficulty can be overcome if bipolar circuits can be made with density comparable to that of MOS circuits. To this end a bipolar technique using five interconnection layers is applied to an ECL (emitter-coupled-logic) gate array containing 53912 equivalent gates on a 7.8-mm*8.2-mm chip. The gate density is 843 gates/mm/sup 2/ for the chip and 1159 gates/mm for the internal cell region. The density results in short interconnections which reduces line delay, the major factor affecting VLSI performance. An emitter-base self-aligned structure with polysilicon electrodes and resistors (ESPER) combined with U-groove isolation with thick field oxide is employed in the device. Chip parameters and circuit schematics are presented.<<ETX>>