Kouichi Usami

Toward long-term retention-time single-electron-memory devices based on nitrided nanocrystalline silicon dots

A memory capacitor with a structure of Si-SiO/sub 2//nc-Si dots/silicon nitride films/SiO/sub 2/ was prepared by means of nc-Si dot deposition followed by N/sub 2/ plasma nitridation processes. The memory device offers dual memory nodes: nc-Si dots and traps in silicon-nitride films. An enlarged memory window in CV characteristics was observed in memory operations, due to the extra traps in silicon-nitrides. The charge-loss rate was found to be much smaller than that of single memory nodes using nc-Si dots only. The provided larger memory window (about twice the width) and longer retention time in the memory operations (three orders of magnitude) are discussed in terms of trap-assisted charging/discharging mechanisms.

Influence of nanocrystal size on the transport properties of Si nanocrystals

In this study, we have investigated the carrier transport mechanism across silicon nanocrystals with the Al/p-Si/Si nanocrystals/Al structure. Sizes of silicon nanocrystals were controlled at diameters of ∼6, ∼8, and ∼11 nm. It is shown that the conductivity σ of silicon nanocrystals, both as-grown and annealed, exhibits σ∝exp[−(T0/T)]1/2 behavior under low electrical fields and over a wide temperature range. The phenomenon of material constant T0 increasing with the decrease of nanocrystal size has been observed. Considering nanocrystal size effect, experimental results can be explained by the hopping-percolation model. The influence of nanocrystal size on transport properties has been discussed. Based on this model, changes in T0 after annealing treatment are attributed to an increase in effective decay length.

The impacts of surface conditions on the vapor-liquid-solid growth of germanium nanowires on Si (100) substrate

The impacts of surface conditions on the growth of Ge nanowires on a Si (100) substrate are discussed in detail. On SiO2-terminated Si substrates, high-density Ge nanowires can be easily grown. However, on H-terminated Si substrates, growing Ge nanowires is more complex. The silicon migration and the formation of a native SiO2 overlayer on a catalyst surface retard the growth of Ge nanowires. After removing this overlayer in the HF solution, high-density and well-ordered Ge nanowires are grown. Ge nanowires cross vertically and form two sets of parallel nanowires. It is found that nanowires grew along ⟨110⟩ directions.

Visible Electroluminescence from Spherical-Shaped Silicon Nanocrystals

We fabricated light emitting diodes (LEDs) using spherically shaped nanocrystalline silicon (nc-Si), which was formed through very high frequency (VHF; 144 MHz) plasma decomposition of SiH4. In addition, we successfully reduced the roughness of the surface and part of the voids separating the dots by finding the adequate annealing conditions. Red electroluminescence was also observed at 12 V with the naked eye at room temperature under forward bias condition. It is suggested that the origin of the electroluminescence (EL) from Si nanocrystals is due to recombination centers in Si nanocrystals by the comparison of EL and photoluminescence spectra.

Integration of Tunnel-Coupled Double Nanocrystalline Silicon Quantum Dots with a Multiple-Gate Single-Electron Transistor

We report on integration of double nanocrystalline silicon quantum dots (nc-Si QDs) of approximately 10 nm in diameter onto the multiple-gate single-electron transistor (SET) used as a highly-sensitive charge polarization detector. The SET with a single charging island is first patterned lithographically on silicon-on-insulator, and the multiple-gate bias dependence of the Coulomb current oscillation is characterized at 4.2 K. The coupling capacitance parameters between the SET charging island and the multiple-gate are estimated and compared with those obtained by using the three-dimensional capacitance simulation. Double nc-Si QDs are then deposited in the immediate vicinity of the charging island of the SET by using the very-high frequency plasma deposition technique. We perform the single-electron circuit simulations and demonstrate that only ±e charge polarization of the double QDs can be sensed as a shift of the Coulomb oscillation peaks.

Position-Controllable Ge Nanowires Growth on Patterned Au Catalyst Substrate

A well position-controllable single Ge nanowire array was grown on patterned Au catalysts substrate by low-pressure chemical vapor deposition. Both transmission electron microscope and X-ray diffraction results indicate that Ge nanowires are single crystalline with diamond structure. By optimizing the electron-beam lithography process, Au patterns with a diameter of 10 nm were prepared by lift-off method. The growth of Ge nanowires can be precisely controlled by adjusting the location of catalysts, which may offer the possibility of in situ fabrication of nanowire devices.

Photoluminescence of Nanocrystalline Silicon Quantum Dots with Various Sizes and Various Phosphorus Doping Concentrations Prepared by Very High Frequency Plasma

Nanocrystalline silicon quantum dots (nc-Si QDs) with various sizes and various doping concentrations were fabricated by supplying different flow rates of silane (SiH4) gas and phosphine (PH3) gas, respectively, under very high frequency (VHF; 144 MHz) plasma. With an increase in the flow rate of SiH4 gas, the mean size of nc-Si QDs decreases, and photoluminescence (PL) measurements and time-resolved photoluminescence (TRPL) measurements confirm that the quantum confinement becomes weaker. For a small amount of doping PH3 gas, termination of dangling bonds at the interface between the crystal core and the oxide shell in the nc-Si QDs could be supposed on the basis of PL and TRPL measurements. In contrast, for a large amount of doping PH3 gas, Auger recombination could dominate the luminescence properties of nc-Si QDs, and it could decrease the PL intensity and shorten the TRPL decay lifetime.

Grounding positions of superconducting layer for effective magnetic isolation in Josephson integrated circuits

Mutual inductances between two superconducting strip lines coupled through a grounded shield layer are evaluated by both experiments and numerical calculation. A conventional superconducting quantum interference device method on a Nb Josephson integrated circuit chip is employed for experiments. Four test circuits are designed to investigate the effects of ground contacts. Grounding the shield layer at one point or at two points located perpendicular to the line direction does not improve the shielding effect, whereas grounding at two points located parallel to the line direction reduced the mutual inductance by 67%. Mutual inductances calculated using an inductance extraction program, FASTHENRY, agree with the experimental results. Numerical results of current distributions in the shield layers demonstrate that the enhanced shielding current improves the magnetic isolation.

Coulomb Blockade Conditions for Detailed Model of Single-Electron Turnstile Device Including Finite Self-Capacitances of Island Electrodes

We propose a detailed model of a single-electron turnstile device in which each island electrode has a finite self-capacitance. The Coulomb blockade (CB) regions are obtained by calculating the free energy of the system, and are graphically presented in the gate-charge versus bias-voltage plane. We confirm the CB regions obtained to be octagonal, instead of the quadrilateral CB regions obtained in the conventional model.

Preparation of YBCO films on sapphire with CeO/sub 2/ deposited by ion beam sputtering

Although sapphire has superior high frequency properties, an adequate buffer layer is required to form a high-Tc film. We deposited a CeO/sub 2/ buffer layer by ion beam sputtering in high oxygen pressure, and investigated the influence of the deposition conditions on the superconducting properties of YBa/sub 2/Cu/sub 3/O/sub 7-y/ (YBCO) films. CeO/sub 2/ films deposited at higher than 600/spl deg/C were c-axis oriented and YBCO films deposited on the top at 700/spl deg/C were also c-axis oriented. T/sub /spl alpha//(R=0)=89 K and J/sub c/>10/sup 6/A/cm/sup 2/ were obtained for a 120 nm thick YBCO film deposited on 50 nm thick CeO/sub 2/ layer. High oxygen pressure /spl sim/1 Pa is desirable. Grain boundary Josephson junctions were also successfully fabricated on bicrystal sapphire substrate. It was found that high pressure ion beam sputtering is a promising method for superconductive electron devices.