Kozo Harada

Study of package warp behavior for high-performance flip-chip BGA

Abstract To meet the future needs of high pin count and high performance, the LSI die and package size of flip-chip BGA (FC-BGA) devices have become larger. As a result, package warpage due to mismatch of the coefficients of thermal expansion among the construction materials has become a more serious problem for package reliability. In this paper, package warpage is successfully measured by a 3-D surface profile method in the temperature range from −55 to 230 °C. Furthermore, the package warpage of FC-BGA was investigated to clarify the effect of the thermomechanical properties of the underfill resin. Based on the results, we constructed a model of the mechanism of package warpage. This paper proposes an optimized underfill resin that can achieve low package warpage and a long fatigue life of the solder bump. The future trends in underfill resin will be to have properties of extremely low elastic modulus and non-linear properties such as creep.

Analysis of solder joint fracture under mechanical bending test

1. Abstract Recently, Electroless-Nickel and Immersion Gold (ENIG) plating has been applied for metalization of package substrate, because of the difficulties of routing for high pin count package. And we have been experienced that ENIG may cause the electrical open failure by some mechanical stress at In-Circuit Test (ICT) after package mount on printed circuit board (PCB), for example. In order to clarify the phenomena of solder joint fracture which causes open failure, we have been performing a four-point bending test and succeeded to optimize the condition of four-point bending test getting same phenomena as actual failure mode. This test procedure will be effective to simulate the reliability of solder joint. For fourpoint bending test, the daisy chained PCB and Flip-Chip BGA (FC-BGA) package which is 1848pin with 45mm body size, l.0mm ball pitch, were used.

Thermo-electromigration phenomenon of solder bump, leading to flip-chip devices with 5,000 bumps

High performance logic devices have rapidly advanced in network system. In order to reply the demand of high pin count and high speed, Flip-chip BGA (FC-BGA) package applied high-density organic substrate has been developed. This package has the superior possibility of flexible bump locations by virtue of high via densities and fine line capabilities of the substrate. The feature of substrate is adopting the stacked method of finer via pitch layers. Utilizing the density, it is possible to either minimize the LSI die size or maximize the number of bumps on the die. Also at the high performance devices, the high current density through the bump is strongly demanded. In order to satisfy the demand and realize the high pin counts devices, thermo-electromigration phenomenon of solder bump is one of the key reliability items. The thermo-electromigration phenomenon of solder bump was investigated to be consisting of three steps as below. At 1/sup st/ step, the lead (Pb) migrates as electron flow under high-density current, and at 2/sup nd/ step, the Under Bump Metals (UBM) migrates and disappears. Finally at 3/sup rd/ step, Aluminum (Al) routing metal migrates and it results in open failure, and from the High Temperature Operating Life (HTOL) results, the life time of solder bump on current density has been estimated theoretically based on Blacks equation. The lifetime was predicted more than 20 years with the current being 160 mA/bump in 220 /spl mu/m pitch cases.