Krishna Belkhale

Timing model extraction of hierarchical blocks by graph reduction

Timing model extractor builds a timing model of a digital circuit for use with a static timing analyzer. This paper proposes a novel method of generating a gray box timing model from gate-level netlist by reducing a timing graph. Previous methods of generating timing models sacrificed accuracy and/or did not scale well with design size. The proposed method is simple, yet it provides model accuracy including arbitrary levels of latch time borrowing and capability to support timing constraints that span multiple blocks. Also, cpu and memory resources required to generate the model scale well with size of the circuit. The generated model can provide a capacity improvement in timing verification by more than two orders of magnitude.

An α-approxmimate algorithm for delay-constraint technology mapping

Variants of delay-cost functions have been used in a class of technology mapping algorithms [1, 2, 3, 4]. We illustrate that in an industrial environment the delay-cost function can grow unboundedly and lead to very large runtimes. The key contribution of this work is a novel bounded compression algorithm. We introduce a concept of delaycost curve, ( -DC-curve) that requires upto exponentially less delay-cost points to be stored compared to that stored by the delay function. We prove that the solution obtained by this exponential compaction of the delay-function is bounded to % of the optimal solution. We also suggest a large set of CAD applications which may bene t from using -DC-curve. Finally, we demonstrate the e ectiveness of our compaction scheme on one such application, namely technology mapping for low power. Experimental results on industrial environment show that we are more than 17 times faster than [2] on certain MCNC circuit.

An /spl alpha/-approximate algorithm for delay-constraint technology mapping

Variants of delay-cost functions have been used in a class of technology mapping algorithms. We illustrate that in an industrial environment the delay-cost function can grow unboundedly and lead to very large runtimes. The key contribution of this work is a novel bounded compression algorithm. We introduce a concept of /spl alpha/ delay-cost curve, (/spl alpha/-DC-curve) that requires up to exponentially less delay-cost points to be stored compared to that stored by the delay function. We prove that the solution obtained by this exponential compaction of the delay-function is bounded to /spl alpha/% of the optimal solution. We also suggest a large set of CAD applications which may benefit from using /spl alpha/-DC-curve. Finally, we demonstrate the effectiveness of our compaction scheme on one such application, namely technology mapping for low power. Experimental results on industrial environment show that we are more than 17 times faster than on certain MCNC circuit.