Krishna C. Saraswat

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies in one single chip is becoming increasingly desirable, for which planar (two-dimensional) ICs may not be suitable. This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occurring a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D chip. Furthermore, one of the major concerns in 3-D ICs arising due to power dissipation problems has been analyzed and an analytical model has been presented to estimate the temperatures of the different active layers. It is demonstrated that advancement in heat sinking technology will be necessary in order to extract maximum performance from these chips. Implications of 3-D device architecture on several design issues have also been discussed with special attention to SoC design strategies. Finally some of the promising technologies for manufacturing 3-D ICs have been outlined.

Interconnect limits on gigascale integration (GSI) in the 21st century

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node.

Two-dimensional thermal oxidation of silicon. II. Modeling stress effects in wet oxides

For pt.I see ibid., vol.ED-34, p.1008-17 (May 1987). The authors propose that the stress from two-dimensional oxide deformation affects the kinetic parameter in the Deal-Grove model (1965). In particular, the viscous stress associated with the nonuniform deformation of the oxide is identified as the fundamental force of retardation. In this model, the stress normal to the Si-SiO/sub 2/ interface reduces the surface reaction rate in both convex and concave surfaces, whereas the stress in the bulk of the oxide (compressive for concave and tensile for convex surfaces) is responsible for the thinner oxides on the concave structures. The model is described by a simplified mathematical formulation made possible by the symmetry in cylindrical structures. Comparisons with experimental data, possible applications, and limitations of the model are also discussed. >

Germanium nanowire field-effect transistors with SiO2 and high-κ HfO2 gate dielectrics

Single-crystal Ge nanowires are synthesized by a low-temperature (275 °C) chemical vapor deposition (CVD) method. Boron doped p-type GeNW field-effect transistors (FETs) with back-gates and thin SiO2 (10 nm) gate insulators are constructed. Hole mobility higher than 600 cm2/V s is observed in these devices, suggesting high quality and excellent electrical properties of as-grown Ge wires. In addition, integration of high-κ HfO2 (12 nm) gate dielectric into nanowire FETs with top-gates is accomplished with promising device characteristics obtained. The nanowire synthesis and device fabrication steps are all performed below 400 °C, opening a possibility of building three-dimensional electronics with CVD-derived Ge nanowires.

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

Germanium MOS capacitors incorporating ultrathin high-/spl kappa/ gate dielectric

For the first time, we have successfully demonstrated the feasibility of integrating a high-permittivity (/spl kappa/) gate dielectric material zirconium oxide into the MOS capacitors fabricated on pure germanium substrates. The entire fabrication process was essentially performed at room temperature with the exception of a 410/spl deg/C forming gas anneal. After processing steps intended to remove the germanium native oxide interlayer between the zirconium oxide dielectric and germanium substrate, an excellent capacitance-based equivalent SiO/sub 2/ thickness (EOT) on the order of 5-8 /spl Aring/ and capacitance-voltage (C-V) characteristics with hysteresis of 16 mV have been achieved. Additionally, excellent device yield and uniformity were possible using this low thermal budget process.

Dopant segregation in polycrystalline silicon

Dopant segregation at grain boundaries in polycrystalline silicon has been investigated. Arsenic, phosphorus, and boron were ion implanted into low‐pressure, chemically‐vapor‐deposited polycrystalline‐silicon films. All films were then annealed at 1000 °C for 1 h, and some were subsequently further annealed at 800, 850, or 900 °C for 64, 24, or 12 h, respectively. For phosphorus and arsenic the room‐temperature resistivity of the films was found to be higher after annealing at lower temperatures. By successively annealing the same sample at lower and higher temperatures, the resistivity would repeatedly increase and decrease, indicating reversible dopant segregation at the grain boundaries. Hall measurements were used to estimate the number of active dopant atoms within the grains and the number of atoms segregated at the grain boundaries as a function of annealing temperature. A theory of segregation in systems of small particles has been developed. Using this theory, the heat of segregation of arsenic and phosphorus in polycrystalline silicon was calculated. For boron no appreciable segregation was observed.

Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope

The main challenges for Tunnel FETs are experimentally demonstrating SS<60 mV/dec, high ON currents and solving their ambipolar behavior. We have experimentally demonstrated a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS<60 mV/dec. Due to small bandgap of s-Ge and the electrostatics of the DG structure, record high drive current of 300 uA/um (the highest ever reported experimentally for a TFET) and a subthreshold slope of ~50 mV/dec was observed. In addition, to address the ambipolar problem and examine the scalability of TFETs, we have developed a sophisticated TFET simulator that uses a Quantum transport model, Non-local BTBT, complete Bandstructure (real and complex) information, and includes all transitions (direct and phonon assisted). Using this simulator, we have studied the scalability of three asymmetric DG TFET configurations (underlapped drain, lower drain doping and lateral heterostructure) in terms of their ability to solve the ambipolar behavior and achieve high ON and low OFF currents.

The effect of fluorine in silicon dioxide gate dielectrics

The effect of post-oxide-growth fluorine incorporation in gate dielectrics is reported. Fluorine was introduced through ion implantation into polysilicon and diffused into the gate oxide, as indicated by SIMS measurements. No great decrease in the breakdown field was observed, although a decrease in charge-to-breakdown was seen. Interface characteristics also improved with medium to high doses of fluoride. High doses were found to grow additional oxide. NMOS FETs showed increased immunity to hot-electron-induced stress. These results are explained by a model wherein fluorine bonds to silicon, and the displaced oxygen grows the additional oxide. >

Activation and diffusion studies of ion-implanted p and n dopants in germanium

We have demonstrated symmetrically high levels of electrical activation of both p- and n-type dopants in germanium. Rapid thermal annealing of various commonly implanted dopant species were performed in the temperature range of 600–850 °C in germanium substrates. Diffusion studies were also carried out by using different anneal times and temperatures. T-SUPREM™ simulations were used to fit the experimental profiles and to extract the diffusion coefficient of various dopants.