Krishnamachar Prasad

A study of thermo-mechanical stress and its impact on through-silicon vias

The BOSCH etch process, which is commonly used in microelectromechanical system fabrication, has been extensively investigated in this work for implementation in through-silicon via (TSV) technology for 3D-microsystems packaging. The present work focuses on thermo-mechanical stresses caused by thermal loading due to post-TSV processes and their impact on the electrical performance of through-silicon copper interconnects. A test vehicle with deep silicon copper-plated comb structure was designed to study and evaluate different deep silicon via etch processes and its effect on the electrical leakage characteristics under various electrical and thermal stress conditions. It has been shown that the leakage current between the comb interconnect structures increases with an increase in sidewall roughness and that it can be significantly lowered by smoothening the sidewalls. It was also shown that by tailoring a non-BOSCH etch process with the normal BOSCH process, a similar leakage current reduction can be achieved. It was also shown through thermo-mechanical simulation studies that there is a clear correlation between high leakage current behavior due to non-uniform Ta barrier deposition over the rough sidewalls and the thermo-mechanical stress induced by post-TSV processes.

Influence of Bosch Etch Process on Electrical Isolation of TSV Structures

Bosch process is widely used in the fabrication of through silicon via (TSV) holes for 3-D integrated circuit and 3-D Packaging applications mainly due to its high silicon etch rate and selectivity to mask. However, the adverse impact on the electrical performance of the TSV due to the sidewall scallops or wavy profile due to the cyclical nature of the Bosch process has not been thoroughly investigated. This paper therefore focuses on the impact of sidewall scallops on the inter-via electrical leakage performance. Based on finite element analysis, this paper describes that the high stress concentration on the dielectric and barrier layers at the sharp scallops can potentially contribute to barrier failure. It is demonstrated that by smoothening the sidewalls of the TSV, the thermo-mechanical stresses on the dielectric and tantalum barrier is significantly reduced. A test vehicle is designed and fabricated with different geometry of deep silicon vias to study the impact of sidewall profile smoothening for different copper diffusion barrier stacks. It is experimentally demonstrated that the inter-via electrical leakage current can be reduced by almost three orders of magnitude when the sidewall roughness is reduced or replaced by a smoother sidewall. It is also indicated that it is sufficient to smoothen the initial few micrometers of the TSV depth by using a non-Bosch etch process. It is concluded that the Bosch etch process can still be used, with all its merits of high etch rate and high etch selectivity, by tailoring a short initial etch step to smoothen the top sidewalls to minimize the adverse effects of the sidewall scallops.

The development of a tapered silicon micro-micromachining process for 3D microsystems packaging

It has been shown that as the aspect ratio of through-silicon vias (TSV) increases, tapering of TSV structure greatly helps in achieving good sidewall coverage for dielectric, barrier and copper seed metal layers to eventually achieve a void-free copper via-filling by electroplating process. In the present work, a novel three-step tapered via etching process has been developed and demonstrated as a viable process for fabricating a void-free through-silicon copper interconnection structure. This paper discusses in great detail about the plasma etch mechanisms responsible for the step-by-step evolution of tapered silicon via the profile angle in the desirable range of 83–87°. It is further shown that the above multi-step etch process enables the formation of void-free copper vias for via depths close to 300 µm.

Characterization of low-temperature bulk micromachining of silicon using an SF6/O2 inductively coupled plasma

The principal aim of this work was to characterize deep silicon etching at sample temperatures well below room temperature, using an SF6/O2?inductively coupled plasma for micro-electro-mechanical systems applications. In this paper, a study of the etch rates and etch profiles of deep silicon trenches has been undertaken for a series of etching parameters, including RF power, sample stage temperature and O2?gas flow rate. Based on the experimental observations, the formation of an SiOxFy passivation layer, the rate of ion collision through the sheath field and the silicon crystallographic orientation are found to be the three main parameters that affect the etching process. In addition, the formation mechanism of ?black silicon? (nanopillar-based Si structures) has also been proposed based on the experimental data and a simple physical model. For the purpose of silicon bulk micromachining, an optimized recipe has been developed that is suitable for the fabrication of high aspect ratio Si cantilevers on silicon-on-insulator-based waveguide wafers.

Computation of the Thermal Effects of Short Circuit Currents on HTS Transformer Windings

The active development of high temperature superconductor (HTS) materials has led to extensive research and development studies of superconducting transformers worldwide. Considerable benefits have been accomplished with the introduction of the HTS transformer such as reduced power loss, size, and transformer weight. However, recent advancement in the design technology has focused on the HTS transformers ability to also perform as a fault current limiter (FCL). This paper presents the computation of the thermal effects of short circuit currents on a non-FCL HTS transformer and demonstrates how it will behave with an HTS-FCL winding conductor.

The Effects of Short-Circuit and Inrush Currents on HTS Transformer Windings

Rapid changes and developments are being witnessed in the transformer design technologies. The phenomenal growth of power systems has put tremendous responsibilities on the industry to supply reliable and cost-effective transformers. The advent of high-temperature superconductor (HTS) materials has increased interest in research and development of superconducting transformers with major projects being carried out worldwide. The major challenges in the design and development of HTS transformers are the modeling of short-circuit and inrush currents the transformer can withstand. Even though HTS technology is claimed to be more efficient, reliable, and eco-friendly, use of HTS transformers must be appropriately verified through the proper modeling of power system network.

Three-phase modeling of HTS transformer in distribution networks

Transformers utilizing high temperature superconductors (HTS) are considered as a timely invention. The number of power transformers age more than 30 years old and nearing retirement is increasing. If this window of opportunity is not grabbed, there would be great reluctance to replace recently installed highly priced capital asset. Major projects of developing HTS transformers are well making progress in the United States, Europe, Japan, Korea and China which indicate the interest. The efforts must have been appropriately verified through the economic interest of the discounted losses. Consequently, it is very important to develop an understanding of the fundamental HTS transformer design issues that can provide guidance for developing practical devices of interest to the electric utility industry. The parameters of HTS transformer need to be validated before any effort is to carry out to model the behaviour of a distribution network under a range of conditions. The predicted performance and reliability of HTS transformers can then be verified through the network modelling and analysis calculation. The ultimate purpose is to furnish electric utilities precise information as to which HTS transformers work under various applications with greater technical efficiency and proven reliability.

Performance analysis of HTS transformer with fault current limiting properties on short circuit current

The advent of High Temperature Superconductor (HTS) materials has increased interest in research and development of superconducting transformers with major projects being carried out worldwide. Several benefits were accomplished with the introduction such as lower power loss, smaller size and lighter weight transformer. However, recent development on HTS transformer has focused on its ability to also function as Fault Current Limiter (FCL). This paper will show the performance of a non-FCL HTS transformer on short circuit current and predict how it will behave with HTS-FCL transformer winding conductor architectures.

Statistical outlook into the physics of failure for copper low-k intra-metal dielectric breakdown

The degradation of low-k dielectrics is analyzed from a trap-assisted tunneling (TAT) current perspective assuming a Poole-Frenkel (P-F) conduction mechanism. A robust probabilistic failure model is developed which accounts for the development of traps at the low-k-SiN capping layer interface which is believed to be the weak link for evolution of low-k dielectric failure mechanisms. The developed model also accounts for the bond breaking phenomenon as dangling bonds are suggested to be the functional form of trap centers during the evolution of the percolation path. The new model is observed to provide an accurate fit to the failure data in the literature. The statistical nature of time-dependent dielectric breakdown (TDDB) failure is shown to be dependent on the definition of failure and based on the conventional definition of catastrophic leakage current increase, we show that the Lognormal distribution is inapplicable and that the Weibull stochastics needs to be used. Statistical analysis of TDDB data clearly indicates the presence of bimodal failure distributions indicating the presence of two failure mechanisms. Further investigation is necessary to uncover the nature and physics governing these different failure mechanisms. A three-parameter Weibull model is suggested to be appropriate for modeling Cu-induced TDDB failures where an incubation time exists for Cu out-diffusion.

Multi-Channel Surface Electromyography Electrodes: A Review

This paper is a review of multi-channel surface electromyography (sEMG) electrode used in the research for investigating the properties of muscles. Over 300 papers from five recognized journals were examined from the year 2000 to 2013 with only 64 stating the use of multi-channel electrodes in their research. The review determined that multi-channel electrodes can be classified as linear array or 2D array electrodes. The 2D array is the basis for developing the high-spatial-resolution sEMG (HSR-sEMG) or high density sEMG (HD-sEMG). The important factors considered in this review of the electrodes are: 1) the material used; 2) the inter-electrode distance; and 3) the configuration for the collection of the electromyography signals. The basic configurations of the sEMG electrodes are monopolar, bipolar, and double differential. It was found that the majority of the linear array electrodes were used to collect either bipolar or double differential signals. The 2D array electrodes were used to collect monopolar signals. The HSR-sEMG electrodes used a normal double differentiating filter, referred to as Laplacian configuration. The HD-sEMG has versatility being able to collect all types of signals, such as monopolar, bipolar, double differential, or signals filtered by Laplacian configuration.