Krishnaswamy Nagaraj

A low supply voltage high PSRR voltage reference in CMOS process

This paper describes a bandgap voltage reference circuit that operates with a 3 V power supply and is compatible with a digital CMOS process. The use of a simple circuit topology results in a small silicon area of 0.07 mm/sup 2/, a power consumption of 1 mW and a high power supply rejection over a wide frequency band. The circuit realizes a temperature coefficient of 85 ppm//spl deg/C and a standard deviation of 20 mV without trimming. >

A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits

A novel switched-capacitor technique for realizing very large time constants is presented. The technique is insensitive to parasitic capacitances and is very area-efficient. It does not require a complicated clocking scheme. The technique yields a complete family of integrators which in turn can be used to realize higher-order filtering functions based on cascaded biquadratic sections or ladder filters. These integrators have been used to implement an experimental 60-Hz notch filter working from a 128-kHz clock. >

A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25-/spl mu/m digital CMOS process

The design of a high-speed analog-to-digital (A/D) converter for hard disk drive read channels is described. The A/D converter uses a flash architecture with an interleaved sample and hold and interpolating comparator pre-amplifiers. It has 6 bits of resolution at full speed as well as a 7 bit mode operating at a lower speed. The 7 bit mode is useful for servo signal processing. This A/D converter has been implemented in a four-level metal single-poly 0.25 /spl mu/m CMOS technology. The device operates at a speed of up to 700 MSamples/s in the 6 bit mode while maintaining a signal-to-noise-plus-distortion rate (SNDR) of greater than 35 dB at input frequencies of up to one-fourth the sampling rate. In the 7 bit mode, the device operates at up to 200 MSamples/s with a SNDR greater than 41 dB. It occupies an active area of 0.45 mm/sup 2/ and consumes less than 187 mW of power.

Constant transconductance CMOS amplifier input stage with rail-to-rail input common mode voltage range

A novel CMOS amplifier input stage with rail-to-rail input common mode voltage range is described. The circuit uses a simple adaptive biasing scheme to provide a constant transconductance over the entire range, facilitating the optimization of the frequency response of the amplifier. >

Large-swing CMOS buffer amplifier

A circuit configuration for a CMOS buffer amplifier is described. The circuit, which is an enhancement of a previously reported buffer amplifier, features a large output voltage swing and a well-controlled quiescent current. A buffer amplifier of this type has been implemented in a 1.5- mu m CMOS technology. The prototype occupies an area of 275 mil/sup 2/. It works with a 5-V supply and can drive more than 4.2 V (peak to peak) in to 300 Omega with a total harmonic distortion of less than 0.025%. >

A 160 MHz analog equalizer for magnetic disk read channels

This prototype filter has five taps and operates at 160 MHz clock rate, dissipating 200 mW with 5 V supply. The filter occupies 1.35 mm/sup 2/ in BiCMOS with 0.8 /spl mu/m CMOS. It uses BiCMOS sample-and-hold (S/H) circuits to derive analog discrete-time samples, and CMOS time shared sign-sign LMS (SS-LMS) for coefficient adaptation. It improves on a previous analog signal shuffling structure by: (a) fast master S/H improves the dynamic performance and reduces effect of clock jitter on timing and gain recovery, (b) additional S/H amplifiers alleviate settling time requirements and reduce power, (c) time-interleaved LMS algorithm permits low-cost and low-power coefficient adaptation. DACs for taps and for dc offset cancellation are on-chip.

Efficient 6-bit A/D converter using a 1-bit folding front end

An efficient analog-to-digital (A/D) converter architecture that uses a 1-bit folding front end is described. The folder is realized using a zero-crossing detector and transmission gates. The problem arising from the nonideality of the folding operation is handled in a special way. The use of a single folder in front rather than the conventional approach of using multiple folders results in a significantly smaller input capacitance. The architecture has been used for realizing a 7S-Msamples/s, 6-bit A/D converter for local-area-network application. The prototype has been implemented in a 0.5-/spl mu/m single-poly, triple-metal digital CMOS technology. It occupies an area of 1 mm/sup 2/ and has a power consumption of 110 mW from a 3.3-V supply.

CMOS amplifiers incorporating a novel slew rate enhancement technique

A novel technique for enhancing the slew rate in CMOS amplifiers is described. The enhancement is provided by an auxiliary circuit which is automatically activated during transients. The main amplifier is not stressed with large currents, thus minimizing power dissipation and avoiding signal swing problems. This technique is quite generic, and can be applied to a variety of amplifier structures. An experimental operational transconductance amplifier incorporating this technique has been fabricated. A slew rate of 1 V/ mu s with a 10000 pF load capacitance has been achieved, while requiring a quiescent power dissipation of less than 1.5 mW.<<ETX>>

A Two-Stage ADC Architecture With VCO-Based Second Stage

This brief describes the design of a two-stage analog-to-digital converter (ADC) with voltage-controlled oscillator (VCO)-based second stage. The advantages of quantizing the first-stage residue in time domain versus traditional voltage domain are presented. The dc gain requirement of the first-stage residue amplifier is relaxed by reference-scaling and reference-recycling schemes. This enables the use of a very simple telescopic cascode amplifier in the gain stage. The second-stage VCO linearity is improved by a differential measurement of VCO frequency. Power consumption in the second stage is reduced by time-to-digital conversion for fine quantization of the VCO phase. Simulation results are presented for the design of a 13-bit 20-Msps ADC in 65-nm CMOS process. The estimated power dissipation of this converter is less than 1 mW.

A Base-band Codec For Digital Cellular Telephony

The authors describe the design of a baseband codec for European and North American digital cellular telephone applications. By integrating all the data conversion circuitry, this chip offers a low-cost, low-power solution to baseband signal processing and control functions. The receive section has two paths to process the in-phase and quadrature-phase components of the signal. Each path consists of a programmable gain amplifier (PGA) and a 10-b sigma-delta analog/digital (A/D) converter. Two 8-b digital/analog (D/A) converters generate the in-phase and quadrature-phase components of the transmit signal. A 9-b digital-analog converter (DAC) and a 10-b DAC are provided to perform auxiliary control functions. The chip is fabricated using a 0.9- mu m CMOS technology and has an area of 21 mm/sup 2/. The average power dissipation is 85 mW. >