Kristel Fobelets

Strained Si/SiGe n-channel MOSFETs: impact of cross-hatching on device performance

The performance of surface channel MOSFET devices depends on the Si/SiO2 interface quality. The present study has examined the Si/SiO2 interface of strained Si n-channel MOSFETs fabricated on a Si/SiGe virtual substrate. Evidence of a variation in the oxidation rate of strained Si along the cross-hatch period is presented. The undulating oxide thickness was found to be accompanied by increased nanoscale roughness at the Si/SiO2 interface for the strained Si surface channel devices compared with conventional MOSFETs. Fluctuations in the strained Si surface channel thickness were additionally caused by the variation in oxidation rate. The control devices exhibited a tighter distribution of electrical characteristics than the strained Si devices due to the non-uniform cross-hatch severity across the Si/SiGe wafer. The results provide strong evidence that significantly enhanced performance of HNMOS surface channel devices is possible through optimization of epitaxial growth methods. Strain in the channel was maintained following device fabrication using a conventional process with a reduced thermal budget.

Capacitances in double-barrier tunneling structures

Capacitances in a double-barrier tunneling structure are calculated for the specific sequential electron tunneling regime. Starting from Luryis (1988) definition of quantum capacitance, the authors model the charge accumulation in the well during the tunneling process using the Fermi-Dirac distribution. Analytical formulas for the total capacitance and conductance are derived. A complete small-signal model is proposed that demonstrates the external capacitance and conductance of the structure and its frequency behavior. The authors show both theoretically and experimentally that the capacitance in a tunneling structure is both bias- and frequency-dependent. >

MOS gated Si:SiGe quantum wells formed by anodic oxidation

We have used electrochemical anodic oxidation to form gate oxides on strained n-channel Si:SiGe quantum wells. The oxides are characterized by current-voltage and capacitance-voltage measurements. Comparison of measured and calculated electron sheet densities in the quantum well, indicates that the oxide growth does not cause degradation of the Si:SiGe material. This is confirmed by low-temperature measurements of the electron mobility and sheet density in the quantum well.

Field-Effect Transistors Using Silicon Nanowires Prepared by Electroless Chemical Etching

Silicon nanowires, prepared by electroless chemical etching, are used to fabricate dual-gate field-effect transistors. The diameters of the nanowires vary from 40-300 nm, with a maximum aspect ratio of ~3000. Titanium silicide contacts are fabricated on single nanowires. An aluminium top-gate, combined with a back-gate, forms a dual-gate transistor. In an n-channel device with a nanowire diameter of ~70 nm, the output characteristics show current saturation, with a maximum current of ~100 nA. A drain-source threshold voltage exists for current flow, controlled by the gate voltage, and assists in device turn-off. The on/off current ratio is ~3000, and the subthreshold swing is ~780 mV/decade.

pnp resonant tunneling light emitting transistor

A pnp bipolar resonant tunneling transistor is realized using a base consisting of an n‐type modulation doped quantum‐well layer next to a double‐barrier tunneling structure. Electrons are injected from the quantum‐well base layer into the tunneling structure, leading to quantum‐well light emission when they recombine with holes from the emitter. This optical output, which is modulated by the base voltage, persists in the negative differential resistance region of the current‐voltage characteristics where the hole current is in oscillation. This opens possibilities for using this transistor as a high frequency electro‐optical heterodyne convertor.

In situ Raman spectroscopy of the selective etching of antimonides in GaSb/AlSb/InAs heterostructures

The in situ real-time monitoring of the selective etching of semiconductor structures with a Raman microprobe system is demonstrated for the first time. The technique that is applied to GaSb/AlSb/InAs heterostructures allows the accurate timing of the etching as well as a study of the chemistry of the etching process and can be applied to many problems in the processing of compound semiconductors. During etching of AlSb a surface layer rich in Sb builds up that slows down the etch rate, whereas GaSb is etched without producing this residue layer. The different etching behaviour of AlSb and GaSb is confirmed by measurements of the etching depth in patterned samples by means of a Dektak stepper. The origin of the antimony layer is explained.

Strained-Si modulation doped field effect transistors as detectors of terahertz and sub-terahertz radiation

Strained-Si modulation doped field effect transistors have been studied as detectors of 0.2 THz and 1.6 THz electromagnetic radiation at room temperature. The difference in the gate voltage dependences for 0.2 THz and 1.6 THz radiation and spatial pattern of the transistor response to focused 1.6 THz radiation confirms that the mechanism of detection is linked to the excitations of the two-dimensional electrons in the device channel.

High density micro-pyramids with silicon nanowire array for photovoltaic applications

We use a metal assisted chemical etch process to fabricate silicon nanowire arrays (SiNWAs) onto a dense periodic array of pyramids that are formed using an alkaline etch masked with an oxide layer. The hybrid micro-nano structure acts as an anti-reflective coating with experimental reflectivity below 1% over the visible and near-infrared spectral regions. This represents an improvement of up to 11 and 14 times compared to the pyramid array and SiNWAs on bulk, respectively. In addition to the experimental work, we optically simulate the hybrid structure using a commercial finite difference time domain package. The results of the optical simulations support our experimental work, illustrating a reduced reflectivity in the hybrid structure. The nanowire array increases the absorbed carrier density within the pyramid by providing a guided transition of the refractive index along the light path from air into the silicon. Furthermore, electrical simulations which take into account surface and Auger recombination show an efficiency increase for the hybrid structure of 56% over bulk, 11% over pyramid array and 8.5% over SiNWAs.

Influence of the Ge concentration in the virtual substrate on the low frequency noise in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors

We report on low frequency noise and field-effect mobility in strained-Si surface n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) grown on relaxed virtual substrates with a Ge concentration varying between 0% and 30%. An increased Ge concentration results in higher intrinsic field-effect mobility, increasing from 380cm2V−1s−1 for the unstrained channel to 865cm2V−1s−1 for the strained-Si MOSFET on 30% relaxed SiGe virtual substrate. However, the higher mobility is traded off for increased substrate leakage currents and increased 1∕f (flicker) noise. It is suggested that flicker noise is due to traps in the oxide layer. The density of traps increases from 2×1017eV−1cm−3 for 0% Ge to 2.3×1018eV−1cm−3 for the 30% Ge virtual substrate.

Impact of virtual substrate quality on performance enhancements in strained Si/SiGe heterojunction n-channel MOSFETs

Abstract The performance of surface channel MOSFET devices is dependent on the Si/SiO 2 interface roughness. This paper examines the performance demonstrated by strained Si/SiGe heterojunction n-channel MOSFET devices (HNMOSFETs) fabricated on ultra-low pressure CVD (ULPCVD) material compared with unstrained Si control devices. The surface channel HNMOSFETs were found to exhibit performance enhancements in terms of transconductance of approximately 135% compared with their Si counterparts. In addition, the electrical characteristics of the HNMOSFETs displayed increased uniformity and improvements in the peak transconductance in excess of 75% compared with equivalent devices fabricated on strained Si/SiGe GS-MBE material. Atomic force microscopy and transmission electron microscopy showed that the favourable characteristics of the ULPCVD strained Si/SiGe devices are due to reduced cross-hatch severity of the ULPCVD material, which is shown to decrease nanoscale roughness at the Si/SiO 2 interface.