Krzysztof Kierzkowski

Distributed embedded-PC-based control and data acquisition system for TESLA cavity controller and simulator

This paper describes an alternative approach for control and data acquisition system to be used in TESLA controller and simulator (SIMCON) boards. The standard VME controller may be replaced with a cheap embedded PC to provide equivalent or even superior functionality. The new approach offers better cost/performance ratio, better scalability of the system and better testability of the SIMCON boards.

Design and simulation of FPGA implementation of a RF control system for the TESLA test facility

This paper presents a new FPGA based solution of the Low Level RF Control System for TESLA Test Facility. The LLRF Control System is responsible for maintaining the constant amplitude and phase of accelerating field in set of accelerators cryomodulaes driven by single klystron. To obtain shorter processing time and less complicated hardware an FPGA based solution was selected. The proposed simulation has been simulated in software, and appeared to be faster and less complex than DSP based solutions.

Fast ADC based multichannel acquisition system for the GEM detector

A novel approach to the Gas Electron Multiplier1 (GEM) detector readout is presented. Unlike commonly used methods, based on discriminators, and analogue FIFOs,[ the method developed uses simultaneously sampling high speed ADCs and advanced FPGA-based processing logic to estimate the energy of every single photon. Such method is applied to every GEM strip signal. It is especially useful in case of crystal-based spectrometers for soft X-rays, where higher order reflections need to be identified and rejected. For the purpose of the detector readout, a novel conception of the measurement platform was developed.

Gigabit optical link test system for RPC muon trigger in the CMS experiment

High-energy experiments like Atlas, Alice, CMS or LHCb at the LHC accelerator at CERN will be performed in very harsh conditions for electronic equipment. High radiation level in the experimental halls causes that commonly available electronic devices do not work properly. A specialized optical transmitter--GOL (Gigabit Optical Link) has been designed at CERN to meet the radiation environment requirements. The design goal was to supply device resistant to high radiation, fast, and being able to transmit data through optical links. Transmitter was designed considering two important characteristics of its work environment: high radiation level and gigabit transmission speed. Proper internal structure of GOL chip allows to minimize single event upsets (SEU) caused by ionizing radiation. Unfortunately, the design does not elimiate SEU completely. This paper presents testing system for the GOL. Its main purpose is testing new prototypes of optical fiber gigabit transmission systems using GOL transmitter and commercial receiver components. The system will be implemented in the CMS experiment for control purposes. It will monitor optical link and transmission quality in the RPC detector. System consits of hardware layer and software layer. Hardware layer, based on Latera FPGA programmable devices. Software has been developed using C++ environment integrated with VME controller hardware.

Optimization of FPGA processing of GEM detector signal

This paper presents analysis of processing method of the signal from Gas Electron Multiplier (GEM) detector acquired in our Field-Programmable Gate Array (FPGA) based readout system. We have found that simple processing of GEM signal received from the charge amplifier, sampled at 100MHz with 10-bit resolution, after low-pass filtering with 15 MHz cut-off frequency, provides accuracy similar to obtained by processing of the raw GEM signal sampled at 2.5 GHz frequency with 8-bit resolution. Even when 3 bits are lost due to long term instability of the detector and analog part of the system - resulting in 7-bit effective resolution, the reasonable accuracy is still preserved. Additionally we have analyzed computational power required to perform the real-time analysis of the GEM signal, taking into consideration resources offered by the FPGA chip used in the prototype platform.

Readout electronics for the GEM detector.

A novel approach to the Gas Electron Multiplier (GEM) detector readout is presented. Unlike commonly used methods, based on discriminators[2],[3] and analogue FIFOs[1], the method developed uses simultaneously sampling high speed ADCs and advanced FPGA-based processing logic to estimate the energy of every single photon. Such method is applied to every GEM strip signal. It is especially useful in case of crystal-based spectrometers for soft X-rays, where higher order reflections need to be identified and rejected[5].

Synchronization methods for the PAC RPC trigger system in the CMS experiment

The PAC (pattern comparator) is a dedicated muon trigger for the CMS (Compact Muon Solenoid) experiment at the LHC (Large Hadron Collider). The PAC trigger processes signals provided by RPC (resistive plate chambers), a part of the CMS muon system. The goal of the PAC RPC trigger is to identify muons, measure their transverse momenta and select the best muon candidates for each proton bunch collision occurring every 25 ns. To perform this task it is necessary to deliver the information concerning each bunch crossing from many RPC chambers to the trigger logic at the same moment. Since the CMS detector is large (the muon hits are spread over 40 ns), and the data are transmitted through thousands of channels, special techniques are needed to assure proper synchronization of the data. In this paper methods developed for the RPC signal synchronization and synchronous transmission are presented. The methods were tested during the MTCC (magnet test and cosmic challenge). The performance of the synchronization methods is illustrated by the results of the tests.

An RPC-based Technical Trigger for the CMS Experiment

In the CMS experiment, sub-detectors may send special trigger signals, called “Technical Triggers”, for purposes like test and calibration. The Resistive Plate Chambers are part of the Muon Trigger System of the experiment, but might also produce a cosmic muon trigger to be used during the commissioning of the detectors, the CMS Magnet Test-Cosmic Challenge and the later running of CMS. The proposed implementation is based on the development of a new board, the RPC Balcony Collector (RBC); the test results on prototypes and their performance during the recent CMS Cosmic Challenge are presented.

Prototype implementation of the embedded PC-based control and DAQ module for TESLA cavity SIMCON

This paper describes the results obtained with the first prototype of the embedded PC (Axis ETRAX LX MCM) based board for control and data acquisition system, to be used in TESLA controller and simulator (SIMCON). This board is a result of the new approach to the architecture of measurement systems, where the VME controller is replaced with the embedded PC, to improve the functionality and to reduce cost of the system. This new concept assures better scalability and testability of the SIMCON board.

Implementation of the data acquisition system for the Resistive Plate Chamber pattern comparator muon trigger in the CMS experiment

This paper presents the implementation of the data acquisition system of the Resistive Plate Chamber (RPC) subdetector in the Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) in CERN. The described readout system connects with the RPC detector, the RPC link system, the RPC trigger system and the CMS data acquisition system and creates one of multiple metrological systems in CMS experiment. The readout system receives the data provided by the multiple channels of the link system, filters out the non-triggered data, encapsulates the data into the standard CMS common data format events and sends them to the global data acquisition system. The main problem in the readout system design was to provide a sufficiently large throughput to reliably transfer the data. The implemented system is the scalable solution based on advanced Field Programmable Gate Arrays (FPGA) technology.