Krzysztof Kołek

FPGA as a part of MS WINDOWS control environment

The attention is focused on the Windows operating system (OS) used as a control and measurementenvironment. Windows OS due to extensions becomes a real-time OS (RTOS).Benefits and drawbacks of typical software extensions are compared. As far as hardwaresolutions are concerned the field programmable gate arrays FPGA technology is proposed toensure fast time-critical operations. FPGA-based parallel execution and hardware implementationof the data processing algorithms significantly outperform the classical microprocessoroperating modes. Suitability of the RTOS for a particular application and FPGA hardwaremaintenance is studied.

Rapid algorithm prototyping and implementation for power quality measurement

This article presents a Model-Based Design (MBD) approach to rapidly implement power quality (PQ) metering algorithms. Power supply quality is a very important aspect of modern power systems and will become even more important in future smart grids. In this case, maintaining the PQ parameters at the desired level will require efficient implementation methods of the metering algorithms. Currently, the development of new, advanced PQ metering algorithms requires new hardware with adequate computational capability and time intensive, cost-ineffective manual implementations. An alternative, considered here, is an MBD approach. The MBD approach focuses on the modelling and validation of the model by simulation, which is well-supported by a Computer-Aided Engineering (CAE) packages. This paper presents two algorithms utilized in modern PQ meters: a phase-locked loop based on an Enhanced Phase Locked Loop (EPLL), and the flicker measurement according to the IEC 61000-4-15 standard. The algorithms were chosen because of their complexity and non-trivial development. They were first modelled in the MATLAB/Simulink package, then tested and validated in a simulation environment. The models, in the form of Simulink diagrams, were next used to automatically generate C code. The code was compiled and executed in real-time on the Zynq Xilinx platform that combines a reconfigurable Field Programmable Gate Array (FPGA) with a dual-core processor. The MBD development of PQ algorithms, automatic code generation, and compilation form a rapid algorithm prototyping and implementation path for PQ measurements. The main advantage of this approach is the ability to focus on the design, validation, and testing stages while skipping over implementation issues. The code generation process renders production-ready code that can be easily used on the target hardware. This is especially important when standards for PQ measurement are in constant development, and the PQ issues in emerging smart grids will require tools for rapid development and implementation of such algorithms.

Semi-Active Suspension Laboratory System

The paper describes the semi-active suspension laboratory system (SAS), built to demonstrate and test a number of control algorithms. The heart of the system is the automotive engineering damper with the restoring force controlled by magnetic field. We use in our apparatus the Lord 1097 magnetorheological (MR) damper manufactured by the American company. MR devices benefit from the ability of MR fluids to rapidly change rheological properties upon exposure to a magnetic field. The main advantage of the SAS is its portability as a demonstrative experimental rig to test control damping algorithms. The damped less oscillations are compared to the On-off damped oscillations of the apparatus. The MR damper provides an effective solution to SAS control in a variety of applications.

A ROBUST REPETITIVE CONTROL SCHEME WITH RELAXED MINIMUM TIME CRITERION

Abstract A repetitive control scheme is proposed for constrained nonlinear optimal control problems. The lower level algorithm adjusts switching times for bang control arcs and parameters of interval polynomial approximations for interior control arcs. It is based on a linearization of optimal controller and performs reduced optimization with changes of control structure. The upper level finds the optimal control and recalculates the linearization each time the deviation from the optimal solution becomes too large. The linearized controller is analytically derived. The upper level uses the MSE method to determine the reference optimal control structure. Simulation and experimental tests show that the proposed approach yields an optimizing nonlinear controller, able both to ensure close to minimum-time point-to-point transition as well as to stabilize the state.

Rapid controller development for a dynamic voltage restorer

This paper addresses the problem of rapid development of real-time controllers for Dynamic Voltage Restorer (DVR). A DVR includes an active rectifier and an inverter, which share the common DC link. The DVR controller has to include both the rectifier and the inverter control parts, and to guarantee the correct cooperation of the components. This causes the control algorithms to be complex. The paper presents the construction of a DVR and describes the details of an example control algorithm. The control policy is developed as Simulink diagram. The rapid development flow describes the steps that directly lead from the Simulink diagram to the DVRs real-time controller. The description of the laboratory DVR setup and the results showing the stabilization of output AC rms value are given. The main advantage of the rapid development path is the ability to focus on the design, validation and testing stages and skip the implementation issues.

Heterogeneous active power filter controller

The paper describes the architecture of a shunt Active Power Filter (APF) controller composed of three components with different characteristics. Heterogeneous components correspond to the variety of tasks expected from the APF controller. Some of the tasks require real-time execution, some of the requirements are specific to the features of general-purpose operating systems, and some require highly responsive timing and precision. The proposed architecture consists of two processors and an FPGA fabric. The processors operate in asymmetric multiprocessing configuration and run respectively real-time kernel and Linux operating system. The presented approach has been successfully applied to APF control.

Velocity estimation for slow motion devices equipped with encoder

This paper addresses the problem of velocity estimation for slow motion elements equipped with encoders. The slow movement causes rare pulses generated from the encoder, rarer than the sampling frequency. In such conditions, the velocity calculation by numeric derivative or Luenbergera observer fails. For that, it is proposed a new velocity estimation algorithm that uses information specific for encoder operating mode. Simulation and real-time experiments have shown a significant reduction in velocity error estimation of the proposed algorithm in comparison to conventional algorithms.

A new current based slip controller for ABS

A laboratory Anti-Lock Brake System (ABS) is examined. The architecture of the ABS system is shown. The real-time experiments related to a control action to stabilize the slip at a certain level are taken into consideration. A new slip control algorithm differs from the previously used approaches. It is based on the measured current of the braking DC motor. The experimental results collected in the real-time for an old (relay) and new (current based) slip control are compared.

Cable Vibration Control Supported by SOC Architecture

Abstract In the paper the System-On-the-Chip (SOC) based on a FPGA circuit is presented to collect input data, perform conditioning and to generate the control signals for the cable system equipped with the MR damper. The FPGA configuration and SOC programming techniques are shown. Experimental results of a semi-active vibration control system controlled by the SOC module are considered. A research is conducted how to mitigate or reduce vibrations by control algorithms.

The FPGA technology in control of Electrical Discharge Machining process

Abstract Electrical Discharge Machining (EDM) is very accurate manufacturing process able to trim any desired shapes in various materials. The proposed measurement and control system comprises a stand-alone FPGA controller, EDM machine and data acquisition system (DAQ) based on standard PC. The stand-alone FPGA controller can operate in an open loop and feedback structures. It enables the interaction with a high-speed A/D converters, differential analog D/A converters and digital, differential incremental encoders inputs. In order to demonstrate the performance of a simple controller an experiments in the closed-loop of EDM system were conducted. The real-time control algorithm runs on the autonomous FPGA system which is equipped with a Spartan II chip [7]. The experimental results are shown and discussed. The unique feature of the investigated FPGA-based controller is reaction time which can be shorter than 1 microsecond.