Krzysztof Poźniak

CCD detectors for wide field optical astronomy

The paper presents the way that colour can serve solving the problem of calibration points indexing in a camera geometrical calibration process. We propose a technique in which indexes of calibration points in a black-and-white chessboard are represented as sets of colour regions in the neighbourhood of calibration points. We provide some general rules for designing a colour calibration chessboard and provide a method of calibration image analysis. We show that this approach leads to obtaining better results than in the case of widely used methods employing information about already indexed points to compute indexes. We also report constraints concerning the technique. Nowadays we are witnessing an increasing need for camera geometrical calibration systems. They are vital for such applications as 3D modelling, 3D reconstruction, assembly control systems, etc. Wherever possible, calibration objects placed in the scene are used in a camera geometrical calibration process. This approach significantly increases accuracy of calibration results and makes the calibration data extraction process easier and universal. There are many geometrical camera calibration techniques for a known calibration scene [1]. A great number of them use as an input calibration points which are localised and indexed in the scene. In this paper we propose the technique of calibration points indexing which uses a colour chessboard. The presented technique was developed by solving problems we encountered during experiments with our earlier methods of camera calibration scene analysis [2]-[3]. In particular, the proposed technique increases the number of indexed points points in case of local lack of calibration points detection. At the beginning of the paper we present a way of designing a chessboard pattern. Then we describe a calibration point indexing method, and finally we show experimental results. A black-and-white chessboard is widely used in order to obtain sub-pixel accuracy of calibration points localisation [1]. Calibration points are defined as corners of chessboard squares. Assuming the availability of rough localisation of these points, the points can be indexed. Noting that differences in distances between neighbouring points in calibration scene images differ slightly, one of the local searching methods can be employed (e.g. [2]). Methods of this type search for a calibration point to be indexed, using a window of a certain size. The position of the window is determined by a vector representing the distance between two previously indexed points in the same row or column. However, experiments show that this approach has its disadvantages, as described below. * E-mail: A.Nowakowski@ire.pw.edu.pl Firstly, there is a danger of omitting some points during indexing in case of local lack of calibration points detection in a neighbourhood (e.g. caused by the presence of non-homogeneous light in the calibration scene). A particularly unfavourable situation is when the local lack of detection effects in the appearance of separated regions of detected calibration points. It is worth saying that such situations are likely to happen for calibration points situated near image borders. Such points are very important for the analysis of optical nonlinearities, and a lack of them can significantly influence the accuracy of distortion modelling. Secondly, such methods may give wrong results in the case of optical distortion with strong nonlinearities when getting information about the neighbouring index is not an easy task. Beside this, the methods are very sensitive to a single false localisation of a calibration point. Such a single false localisation can even result in false indexing of a big set of calibration points. To avoid the above-mentioned problems, we propose using a black-and-white chessboard which contains the coded index of a calibration point in the form of colour squares situated in the nearest neighbourhood of each point. The index of a certain calibration point is determined by colours of four nearest neighbouring squares (Fig.1). An order of squares in such foursome is important. Because the size of a colour square is determined only by the possibility of correct colour detection, the size of a colour square can be smaller than the size of a black or white square. The larger size of a black or white square is determined by the requirements of the exact localisation step which follows the indexing of calibration points [3]. In this step, edge information is extracted from a blackand-white chessboard. This edge information needs larger Artur Nowakowski, Wladyslaw Skarbek Institute of Radioelectronics, Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, A.Nowakowski@ire.pw.edu.pl Received February 10, 2009; accepted March 27, 2009; published March 31, 2009 http://www.photonics.pl/PLP

FPGA based charge fast histogramming for GEM detector

This article presents a fast charge histogramming method for the position sensitive X-ray GEM detector. The energy resolved measurements are carried out simultaneously for 256 channels of the GEM detector. The whole process of histogramming is performed in 21 FPGA chips (Spartan-6 series from Xilinx) . The results of the histogramming process are stored in an external DDR3 memory. The structure of an electronic measuring equipment and a firmware functionality implemented in the FPGAs is described. Examples of test measurements are presented.

Versatile prototyping platform for Data Processing Boards for CBM experiment

The CBM experiment is one of the experiments prepared at the FAIR Facility in Darmstadt. The Data Processing Boards (DPB) are an important component of the CBM readout chain. Before the final, production versions of DPB may be designed, it is important to create a prototyping platform, to test and select appropriate hardware and firmware solutions. The Kintex based AMC FMC Carrier (AFCK) board is a versatile and open solution fulfilling those requirements, offering configurable high-speed (up to 10 Gbps) connectivity. The paper describes the AFCK hardware, the firmware architecture, and the IP cores developed for different DPB prototyping tasks. Due to its versatility and openness the AFCK may be reused in other experiments.

Data acquisition methods for GEM detectors

This paper overviews various methods of data acquisition from GEM detectors. Presented are currently working systems in tokamaks. The data acquisition methods are divided into two parts. First part, devoted to analog signal processing , describes different approaches for signals acquisition, i.e. pulse amplifying and shaping, ASIC use, delay lines. Digital data acquisition part describes presently used high speed interfaces and system standards. Described are also different approaches for data handling, i.e. online analysis, data reduction, system topologies.

Fast modular data acquisition system for GEM-2D detector

A novel approach to two dimensional Gas Electron Multiplier (GEM) detector readout is presented. Unlike commonly used methods, based on discriminators and analogue FIFOs, the method developed uses simulta- neously sampling high speed ADCs with fast hybrid integrator and advanced FPGA-based processing logic to estimate the energy of every single photon. Such a method is applied to every GEM strip / pixel signal. It is especially useful in case of crystal-based spectrometers for soft X-rays, 2D imaging for plasma tomography and all these applications where energy resolution of every single photon is required. For the purpose of the detector readout, a novel, highly modular and extendable conception of the measurement platform was developed. It is evolution of already deployed measurement system for JET Spectrometer.

Optimization of FPGA processing of GEM detector signal

This paper presents analysis of processing method of the signal from Gas Electron Multiplier (GEM) detector acquired in our Field-Programmable Gate Array (FPGA) based readout system. We have found that simple processing of GEM signal received from the charge amplifier, sampled at 100MHz with 10-bit resolution, after low-pass filtering with 15 MHz cut-off frequency, provides accuracy similar to obtained by processing of the raw GEM signal sampled at 2.5 GHz frequency with 8-bit resolution. Even when 3 bits are lost due to long term instability of the detector and analog part of the system - resulting in 7-bit effective resolution, the reasonable accuracy is still preserved. Additionally we have analyzed computational power required to perform the real-time analysis of the GEM signal, taking into consideration resources offered by the FPGA chip used in the prototype platform.

TRIDAQ systems in HEP experiments at LHC accelerator

The paper describes Trigger and Data Acquisition (TRIDAQ) systems of accelerator experiments for High Energy Physics. The background for physics research comprises assumptions of the Standard Model theory with basic extensions. On this basis, a structure of particle detector system is described, with emphasis on the following functional blocks: Front-End Electronics, Trigger and DAQ systems. The described solutions are used in the LHC experiments: ATLAS, ALICE, CMS and LHCb. They are also used in other accelerator experiments. Data storage and processing functionality is divided into two hardware systems: Trigger and Data Acquisition, that are dependent on each other. High input data rate impose relevant choices for the architecture and parameters of both systems. The key parameters include detailed system structure and its overall latency. Trigger structure is defined by the physics requirements and the storage capability of DAQ system. Both systems are designed to achieve the highest possible space and time resolution for particle detection. Trigger references are reviewed [1-43] as well as chosen accelerator research efforts origination in this country [44-83].

A plug-in to Eclipse for VHDL source codes: functionalities

The paper presents an original application, written by authors, which supports writing and edition of source codes in VHDL language. It is a step towards fully automatic, augmented code writing for photonic and electronic systems, also systems based on FPGA and/or DSP processors. An implementation is described, based on VEditor. VEditor is a free license program. Thus, the work presented in this paper supplements and extends this free license. The introduction characterizes shortly available tools on the market which serve for aiding the design processes of electronic systems in VHDL. Particular attention was put on plug-ins to the Eclipse environment and Emacs program. There are presented detailed properties of the written plug-in such as: programming extension conception, and the results of the activities of formatter, re-factorizer, code hider, and other new additions to the VEditor program.

GEM detector development for tokamak plasma radiation diagnostics: SXR poloidal tomography

An increased attention to tungsten material is related to a fact that it became a main candidate for the plasma facing material in ITER and future fusion reactor. The proposed work refers to the studies of W influence on the plasma performances by developing new detectors based on Gas Electron Multiplier GEM) technology for tomographic studies of tungsten transport in ITER-oriented tokamaks, e.g. WEST project. It presents current stage of design and developing of cylindrically bent SXR GEM detector construction for horizontal port implementation. Concept to overcome an influence of constraints on vertical port has been also presented. It is expected that the detecting unit under development, when implemented, will add to the safe operation of tokamak bringing creation of sustainable nuclear fusion reactors a step closer.

Design of versatile ASIC and protocol tester for CBM readout system

Silicon Tracking System (STS), Muon Chamber (MUCH) and Transition Radiation Detector (TRD) subdetectors in the Compressed Baryonic Matter (CBM) detector system at Facility for Antiproton and Ion Research (FAIR) use the same innovative protocol ensuring reliable synchronization of the communication link between the controller and the front-end ASIC, transmission of time-deterministic commands to the ASIC and efficient readout of data. The paper describes the FPGA-based tester platform which can be used both for the verification of the protocol implementation in a front-end ASIC at the design stage, and for testing of the produced ASICs. Due to its modularity, the platform can be easily adapted for different integrated circuits and readout systems.