Kuk Jin Chun

A 2.3GHz linearized CMOS power amplifier with AM-AM and AM-PM distortion correction

A linearized 2.3GHz CMOS power amplifier with AM-AM and AM-PM distortion correction is presented. The varactors are used at the driver amplifier load to correct the phase distortion and gate bias control of the PA to compensate the amplitude distortion. The proposed CMOS PA has been implemented in 0.13µm CMOS technology. The measured results show that P1dB is increased 1.6dB and PAE is improved from 5.5% to 9% at the condition of -28dB EVM, respectively.

As Preamorphization of the Predeposited Amorphous Si Layer for the Formation of the Silicided Ultra Shallow p^+-n Junction

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si consumption phenomenon during silicidation. We can solve these problems by As preamorphization of the predeposited amorphous Si layer. The predeposited amorphous Si layer made the junction depth decrease to nearly the thickness value of the layer and was effectively utilized as the consumed Si source during Ti silicidation. This method was applied to the actual fabrication of the PMOSFET (p-channel metal oxide semiconductor field effect transistor) through the SES (selectively etched Si) technology.

Properties of the p^+ poly-Si Gate Fabricated Using the As Preamorphization Method

In a deep submicron p-channel metal oxide field effect transistor (PMOSFET), the importance of the p+ poly-Si gate with less boron penetration and higher conductivity increases. With As implantation prior to B+ implantation, the conductivity of the p+ poly-Si gate was improved and the boron penetration was suppressed. These phenomena can be attributed to the enhancement of the grain growth in the As-preamorphized film and the retarded boron diffusion during annealing. DC conductivity of the film preamorphized by As+ ions at 180 keV and 4×1014 cm-2 was about 36% higher than that of the B implanted film without As preimplantation, in spite of the carrier compensation effect. Cross-sectional transmission electron microscopy (XTEM) micrographs show the bilayer with an upper layer of larger grain size ( ~0.22 µm) and a lower layer of smaller grain size ( ~0.03 µm) in the preamorphized and annealed film.

Ti-Silicided Ultra Shallow p+-n Junction Formation by As-Preamorphization through Pre-Deposited Amorphous Si Layer

Major limiting factors in the linear scaling down of the shallow source/drain junction are the boron channeling effect and the Si consumption phenomena during the silicidation. We can approach to solve these problems using the As-preamorphization method through the pre-deposited amorphous Si layer. The pre-deposited amorphous Si layer made the junction depth shorten as much as the thickness of the layer and was effectively utilized for the consuming Si source during Ti silicidation. This method was practically applied to fabricate the PMOSFET(WL=20I0.3pm) through the SES(selectively etched Si) technology.