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Dive into the research topics where Kunal Ravindra Goray is active.

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Featured researches published by Kunal Ravindra Goray.


Journal of Electronic Packaging | 2006

Experimental Characterization of Monotonic and Fatigue Delamination of Novel Underfill Materials

Saketh Mahalingam; Kunal Ravindra Goray; Sandeep Tonapi; Suresh K. Sitaraman

No-flow underfill materials reduce assembly processing steps and can potentially be used in fine-pitch flip chip on organic board assemblies. Such no-flow underfills, when filled with nano-scale fillers, can significantly enhance the solder bump reliability, if the underfills do not prematurely delaminate or crack. Therefore, it is necessary to understand the risk of underfill delamination during assembly and during further thermal excursions. In this paper, the interface between silicon nitride (SiN) passivation and a nano-filled underfill (NFU) material is characterized under monotonic as well as thermo-mechanical fatigue loading, and fracture parameters have been obtained from such experimental characterization. The passivation-underfill interfacial delamination propagation under monotonic loading has been studied through a fixtureless residual stress induced decohesion (RSID) test. The propagation of interfacial delamination under thermo-mechanical fatigue loading has been studied using sandwiched assemblies and a model for delamination propagation has been developed. The characterization results obtained from this work can be used to assess the delamination propagation in flip-chip assemblies. Though the methods presented in this paper have been applied to nano-filled, no-flow underfill materials, their application is not limited to such materials or material interfaces.


intersociety conference on thermal and thermomechanical phenomena in electronic systems | 2004

Design of underfill materials for lead free flip chip applications

Saketh Mahalingam; Kunal Ravindra Goray; Ashutosh Joshi

The reliability of flip chips (FC) is enhanced several orders of magnitude by the introduction of an underfill material between the chip and the substrate. The design of such underfill materials is not trivial due to the varied failure mechanisms that occur in the underfilled configuration. Reliability of underfilled flip chips not only depends on the thermo-mechanical properties of the underfill but also the processing conditions. Hence, the design of an underfill material must involve the development of the optimal processing conditions for the underfill material. Legislation against the use of lead in electronics has led to extensive research on alternative alloy systems and such a change will lead to a number of modifications at the various levels of packaging. Underfill materials are no exception to such a change. The differences between the designs of the underfill material for a lead solder based and a lead-free solder based package are examined in this paper. Among the different lead free solder options, the tin-3.9%silver-0.8%copper (SAC) alloy was compared against the standard eutectic tin-lead solder. Higher CTE and lower modulus resulted in shorter lifetimes of the package for either solder alloy. The SAC alloy does not plastically deform as much as the eutectic tin-lead solder and its creep deformation is less at lower stresses and more at higher stresses than the tin-lead solder. Overall, when subjected to the -55/spl deg/C to 125/spl deg/C cycle, the SAC exhibited superior performance than the tin-lead solder. This meant that a flip chip package with SAC alloy can last as long as a tin-lead solder based package while using a higher CTE underfill than the tin-lead solder package. However, it would be incorrect to conclude that SAC will always have smaller deformation than the tin-lead solder. Firstly, the processing conditions, especially in a no-flow underfilling scenario are different. This requires the underfill not only to provide fluxing action at higher reflow temperatures but also to withstand the higher residual stresses during subsequent cooldown. Secondly, the creep behavior of the SAC alloy is poorer at higher stress levels and applications operating at such stress levels would place more demands on the underfill.


Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology | 2006

Thermal Shock Testing as a Reliability Qualification Test for Lead-Free Solder

Kunal Ravindra Goray; Saketh Mahalingam; Amit Mukesh Shah; Abhijit Dasgupta

Accelerated thermal cycling tests are used to ascertain the reliability of solder interconnects in electronics assemblies. These tests typically last a few months and therefore, are highly resource intensive. Thermal shock tests on the other hand are faster but have been found to be ineffective in accelerating thermal cycling failures for eutectic tin lead solder. In this paper, thermal shock testing is proposed as an alternative to conventional thermal cycling testing for lead-free solder interconnects using Sn, Ag and Cu (SAC) solder. Results from the thermal shock and thermal cycling testing of Ball-Grid-Array (BGA) components are presented. Failure analyses of the solder joints reveal the failure mode for thermal shock in comparison to thermal cycling testing. Numerical modeling results for the thermal cycling and thermal shock testing for lead free and eutectic lead solder are then presented and discussed. The simulation results agree with the experiments and theory is proposed to account for the similar trends between thermal cycling and thermal shock testing for lead free solder.Copyright


Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology | 2005

Reliability of Underfilled Chip Scale Packages Attached With Heat Sink

Saketh Mahalingam; Ashutosh Joshi; Joseph Lacey; Kunal Ravindra Goray

Chip Scale Packages (CSP) are ideal intermediates between Direct Chip Attach (DCA) and Ball Grid Array (BGA) technologies in terms of both size and cost. Depending upon the application, chip scale packages are either underfilled for better solder joint reliability or are attached with a heat sink to keep the operating temperature of the chip under control. In many applications, as discussed in this paper, both an underfill and a heat sink are required. Quite expectedly the addition of two more materials, heat sink and adhesive, in the board level assembly results in fresh reliability concerns. In particular, the requirements on the underfill material and the heat sink attach adhesive are more rigorous and needless to say, a proper understanding of process and material issues is needed to make such a choice. The inelastic strains experienced by the solder joint (related to the underfill) and the peeling stresses at the heat sink attach adhesive interfaces (related to the thermal adhesive) are used as metric for comparing the number of material choices that are available. Based on the results, it is shown that it is important to choose materials that are thermo-mechanically matched with the rest of the system.Copyright


Archive | 2004

Electronically controlled grade crossing gate system and method

Mallikarjun Shivaraya Kande; Vidyadhar Kottisa; David Michael Davenport; Pradeep Vijayan; Kuna Venkat Satya Rama Kishore; Kunal Ravindra Goray; Raju Mogaveera; Ramasamy Anbarasu


Archive | 2010

System and method for mounting a cooling device and method of fabrication

Mehmet Arik; Charles Erklin Seeley; Yogen Vishwas Utturkar; William Edward Burdick; Kunal Ravindra Goray; Stanton Earl Weaver


Archive | 2005

System and method for operating an exhaust gas sensor system

David Shaddock; Ganapathisubbu Sethuvenkatraman; Kunal Ravindra Goray


Archive | 2011

MAGNETOSTRICTIVE SENSOR SYSTEM AND METHOD

Pekka Tapani Sipilä; Kunal Ravindra Goray; Marko Baller; Simon Herbert Schramm; Christof Martin Sihler


Archive | 2010

System and method for inspection of stator vanes

Sheri George; Vinay Bhaskar Jammu; Vinod Padmanabhan Kumar; Chayan Mitra; Kunal Ravindra Goray; Achalesh Kumar Pandey; Ravi Yoganatha Babu; Bhasker Rao Keely; Munish Vishwas Inamdar


Archive | 2006

Ablative Circuit Interruption Device

Thangavelu Asokan; Sunil Srinivasa Murthy; Kunal Ravindra Goray; Adnan Kutuhuddin Bohori

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Saketh Mahalingam

Georgia Institute of Technology

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