Kunitoshi Nishijo

Adaptive Channel Estimation using Cyclic Prefix for Single Carrier Wireless System with FDE

It has been verified recently that single carrier cyclic prefixed (SC-CP) with frequency domain equalizer (FDE) is a promising system for mobile communication and robust channel estimation is needed to build the equalizers weight. Conventional SC-CP wireless system uses training sequences that put in every packet to get the channel information. This increases the overhead of the system. Here we propose a new channel estimation technique by employing cyclic prefix (CP) to maintain both system performance and throughput for this SC wireless system, with 300 kHz bandwidth and 1.6 Mbps throughput. The CP, which is inserted between blocked data to avoid inter-block interference (IBI), can be viewed as a source of channel information. If we can estimate the transmitted CP by conventional way, we can continue to estimate the channel adaptively. The simulation results show that the proposed channel estimation technique can maintain the system performance and gives 14,9% higher throughput compared with the conventional one when the number of packet is increased.

Design of 600Mbps 4×2 MIMO-OFDM Wireless LAN System and Its FPGA Implementation

This paper presents a model-based register transfer level (RTL) design of a 4times2 multiple-inputs multiple-outputs (MIMO)-orthogonal frequency domain multiplexing (OFDM) wireless communication systems transmitter and its field programmable gate array (FPGA) implementation. This system provides a maximum of 600 Mbps with 20 meter of propagation distance using 80 MHz baseband bandwidth with 4times2 MIMO scheme.

FPGA Implementation of 3Mbps Single Carrier Mobile Wireless System with 1MHz Bandwidth

In this paper, we present a FPGA implementation of single carrier (SC) wireless system with frequency domain equalization (FDE) to overcome the effects of multipath fading channels. We propose a new packet format for this wireless system to reduce the error of channel estimation that occurs in the last part of the packet caused by time fluctuation of the channel. Our targets are veracity 15 km/h and 3 Mbps data rate under 1 MHz bandwidth. Simulation results show that our proposed system can work in severe multipath fading with 33 Hz Doppler shift (15 km/h) and 6 ppm frequency offset environment. The logic synthesis result meets the specification.