Kunta Yoshikawa

High Efficiency Silver-Free Heterojunction Silicon Solar Cell

In this work, we present the results of the replacement of silver screen printing on heterojunction crystalline silicon (c-Si) solar cells with a copper metallization scheme that has the potential to reduce the manufacturing cost while improving their performance. We report for the first time silver-free heterojunction c-Si solar cells on 6-in. wafers. The conversion efficiency reached is a record 22.1% for c-Si technology for this wafer size (Voc = 729 mV, Jsc = 38.3 mA/cm2, FF= 79.1%). The total power generated is more than 5 W for 1-sun illumination, which is a world record. Heat-damp reliability tests show comparable performance for mini-modules fabricated with copper metalized as for conventional silver screen printed heterojunction c-Si solar cells.

6 inch High efficiency back contact crystalline Si solar cell applying heterojunction and thinfilm technology

We have developed a 6 inch heterojunction interdigitated back contact (HJBC) solar crystalline Si cell by applying our heterojunction technology and thinfilm technology. To form rear junction and front side passivation, we applied our heterojunction technology that allows efficiency of 24.5% with top/rear contact heterojunction solar cell. To secure this high quality passivation during the HJBC solar cell fabrication process, we have developed deposition technology of insulator layer originally used in thinfilm silicon solar cells. Furthermore, new structure has been designed to drastically suppress the rear electrode resistance. By adapting all these technologies, our HJBC solar cell has reached conversion efficiency of 24.91% independently confirmed at AIST (VOC=737 mV, ISC=10.07 A, FF=80.2 %, PMAX=5.95 W) under 1 sun illumination by total area measurement (239.0 cm2).

Optimization of Post-Texturization Cleans for Heterojunction Solar Cells

Solar cells employing heterojunction emitters of amorphous silicon (a-Si) on a monocrystalline silicon (c-Si) substrate have demonstrated high efficiencies without requiring high-temperature processing [. An example of such a cell structure is shown in Figure 1. It has been found that the cell efficiency can be boosted by inserting a thin undoped (intrinsic) a-Si layer between the a-Si emitter and the c-Si substrate. The thin intrinsic layer provides very good passivation of interface defects, thus reducing the surface recombination velocity.