Kwang-Jin Koh

0.13-

Two 4-bit active phase shifters integrated with all digital control circuitry in 0.13-mum RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter for quadrature signaling with minimum loss and wide operation bandwidth. Both phase shifters can change phases with less than about 2 dB of RMS amplitude imbalance for all phase states through an associated DAC control. For the X- and Ku-band phase shifter, the RMS phase error is less than 10o over the entire 5-18 GHz range. The average insertion loss ranges from to at 5-20 GHz. The input for all 4-bit phase states is typically at -5.4 plusmn1.3 GHz in the X- and Ku-band phase shifter. The K-band phase shifter exhibits 6.5-13 of RMS phase error at 15-26 GHz. The average insertion loss is from 4.6 to at 15-26 GHz. The input of the K-band phase shifter is at 24 GHz. For both phase shifters, the core size excluding all the pads and the output 50 Omega matching circuits, inserted for measurement purpose only, is very small, 0.33times0.43 mm2 . The total current consumption is 5.8 mA in the X- and Ku-band phase shifter and 7.8 mA in the K-band phase shifter, from a 1.5 V supply voltage.

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This paper demonstrates a 16-element phased-array transmitter in a standard 0.18-mum SiGe BiCMOS technology for Q-band satellite applications. The transmitter array is based on the all-RF architecture with 4-bit RF phase shifters and a corporate-feed network. A 1:2 active divider and two 1:8 passive tee-junction dividers constitute the corporate-feed network, and three-dimensional shielded transmission-lines are used for the passive divider to minimize area. All signals are processed differentially inside the chip except for the input and output interfaces. The phased-array transmitter results in a 12.5 dB of average power gain per channel at 42.5 GHz with a 3-dB gain bandwidth of 39.9-45.6 GHz. The RMS gain variation is < 1.3 dB and the RMS phase variation is < for all 4-bit phase states at 35-50 GHz. The measured input and output return losses are < -10 dB at 36.6-50 GHz, and <-10 dB at 37.6-50 GHz, respectively. The measured peak-to-peak group delay variation is plusmn 20 ps at 40-45 GHz. The output P-1dB is -5plusmn1.5 dBm and the maximum saturated output power is - 2.5plusmn1.5 dBm per channel at 42.5 GHz. The transmitter shows <1.8 dB of RMS gain mismatch and < 7deg of RMS phase mismatch between the 16 different channels over all phase states. A - 30 dB worst-case port-to-port coupling is measured between adjacent channels at 30-50 GHz, and the measured RMS gain and phase disturbances due to the inter-channel coupling are < 0.15 dB and < 1deg, respectively, at 35-50 GHz. All measurements are obtained without any on-chip calibration. The chip consumes 720 mA from a 5 V supply voltage and the chip size is 2.6times3.2 mm2.

m CMOS Phase Shifters for X-, K u -, and K-Band Phased Arrays

This paper demonstrates an 8-element phased array receiver in a standard 0.18-mum SiGe BiCMOS (1P6M, SiGe HBT ft ap 150 GHz) technology for X- and Ku-band applications. The array receiver adopts the All-RF architecture, where the phase shifting and power combining are done at the RF level. With the integrations of all the digital control circuitry and ESD protection for all I/O pads, the receiver consumes a current of 100 ~ 200 m A from a 3.3 V supply voltage. The receiver shows 1.5 ~ 24.5 dB of power gain per channel from a 50 Omega load at 12 GHz with bias current control, and an associated NF of 4.2 dB (@ max. gain) to 13.2 dB (@ min. gain). The RMS gain error is < 0.9 dB and the RMS phase error is < 6deg at 6-18 GHz for all 4-bit phase states. The measured group delay is 162.5 plusmn 12.5 ps for all phase states at 6-18 GHz. The RMS phase mismatch and RMS gain mismatch among the eight channels are < 2.7deg and 0.4 dB, respectively, for all 16 phase states, over 6-18 GHz. The 8-element array can operate instantaneously at any center frequency and with a wide bandwidth (3 to 6 GHz, depending on the center frequency) given primarily by the 3 dB gain variation in the 6-18 GHz range. To our knowledge, this is the first demonstration of an All-RF phased array on a silicon chip with very low RMS phase and gain errors at 6-18 GHz. The chip size is 2.2 times 2.45 mm2 including all pads.

A Millimeter-Wave (40–45 GHz) 16-Element Phased-Array Transmitter in 0.18-

Subharmonically pumped frequency down- and upconversion circuits are implemented in 0.18-/spl mu/m mixed-mode CMOS technology for 2-GHz direct-conversion WCDMA transceiver applications. These circuits operate in quadrature double-balanced mode and a required octet-phases (0/spl deg/, 45/spl deg/, 90/spl deg/, 135/spl deg/, 180/spl deg/, 225/spl deg/, 270/spl deg/, and 315/spl deg/) local oscillator (LO) signal comes from an active multiphases LO generator composed of a polyphase filter and active 45/spl deg/ phase shifting circuits. For linearity improvement, predistortion compensation and negative feedback schemes are used in the frequency down- and upconversion circuits, respectively. The downconverter achieves a conversion voltage gain of 20 dB (to 1-M/spl Omega/ load), 4-dBm IIP3 (18-dBm OIP3 to 50-/spl Omega/ load), 41-dBm IIP2 and 8.5-dB DSB NF at 1-MHz IF frequency, consuming 13.4 mA from 1.8-V supply, in the WCDMA Rx band (2110-2170 MHz). The upconverter, operating as two switched gain modes in the WCDMA Tx band (1920-1980 MHz), consumes 19.4 mA from 1.8-V supply and shows 14.5-dB conversion power gain, 15 -dBm OIP3 (0.5-dBm IIP3) and -11 dBm P/sub 1dB/ at maximum gain mode. At minimum gain mode, it realizes -0.3-dB conversion loss, 10.7-dBm OIP3 (11-dBm IIP3) and 0-dBm P/sub 1dB/, respectively. 3GPP WCDMA modulation tests are performed for both up- and downconversion circuits and the results are discussed in this paper.

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A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18-mum SiGe BiCMOS technology for Q-band (30-50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an IIP3 of -13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8-44 GHz. The rms gain and phase errors are les1.2 dB and les8.7deg for all 4-bit phase states at 30-50 GHz. The beamformer also results in les0.4 dB of rms gain mismatch and les2deg of rms phase mismatch between the four channels. The channel-to-channel isolation is better than -35 dB at 30-50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is 1.4times1.7 mm2 including all pads and CMOS control electronics.

m SiGe BiCMOS Technology

This paper presents a Ku-band SiGe BiCMOS phased array receive chip capable of forming four-simultaneous beams from two antenna inputs. The design is based on the all-RF architecture with 4-bit active phase shifters and 4-bit variable gain amplifiers in each channel. The four-beam chip results in a gain of 4-6 dB per channel at 13-15 GHz, a noise figure of 10-11 dB, a worst case input P1 dB of -14.3 dBm per channel (input third-order intercept point of -7 dBm), and an rms phase and gain error of < 12° and 1.5 dB, respectively. A gain control of 17 dB is also achieved with a phase change of < 5°. The four-beam chip was tested using two input signals and results in a gain of 9-11 dB at 13-15 GHz. The on-chip isolation between the channels has been fully characterized and is > 40 dB at 13-15 GHz. The chips can operate over an instantaneous bandwidth of > 1 GHz at any frequency from 13 to 15 GHz, and the four beams can be at the same frequency if required. With all digital control circuitry and electrostatic discharge protection for all I/O pads, the chip occupies an area of 2.4 × 4.3 mm2 and consumes 520 mA at 3.5-V supply voltage. To our knowledge, this is the first demonstration of an all-RF phased array silicon chip capable of producing four-simultaneous beams from two different antennas or four-simultaneous beams of different polarizations from a dual polarization antenna. The application areas are in satellite communications and defense systems.

An X- and K u -Band 8-Element Phased-Array Receiver in 0.18-

Phased arrays allow electronic scanning of the antenna beam. However, these phased arrays are not widely used due to a high implementation cost. This article discusses the advantages of the RF architecture and the implementation of silicon RFICs for phased-array transmitters/receivers. In addition, this work also demonstrates how silicon RFICs can play a vital role in lowering the cost of phased arrays.

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This paper presents a 6–18 GHz active 5-bit phase shifter in 0.18-µm SiGe BiCMOS technology based on a phase interpolation technique. An L-C resonance-based quadrature all-pass filter generates the I/Q reference signal with high I/Q accuracy over a wide bandwidth, and integrated current-mode DACs control the I/Q amplitudes to achieve 5-bit phase resolution. The phase shifter shows 19.5 dB of power gain with < 1.1 dB of RMS gain variation for all 5-bit phase states at 12 GHz, and the 3-dB gain bandwidth is 7.5–15.2 GHz. The measured RMS phase error is < 3o at 6.4–10.2 GHz and < 5.6° at 6–18 GHz achieving greater than 5-bit accuracy. Within the 3-dB gain bandwidth, the NF ranges from 4 to 5.7 dB and the NF variation is ±0.12 dB for all phase states. The total current consumption is 18.7 mA (phase shifter core: ∼ 3 mA) from a 3.3 V supply voltage and overall chip size is 1.2×0.75 mm2 (phase shifter core: 0.45×0.35 mm2).

SiGe BiCMOS Technology

This paper presents the design and analysis of an improved wideband in-phase/quadrature (I/Q) network and its implementation in a wideband phased-array front-end. It is found that the addition of two resistors (Rs) in the all-pass I/Q network results in improved amplitude and phase performance versus capacitance loading and frequency, which is essential for wideband millimeter-wave applications. A prototype 60-80-GHz phased-array front-end based on 0.13-μm SiGe BiCMOS is demonstrated using the improved quadrature all-pass filter and with 4-bit phase-shifting performance at 55-80 GHz. Application areas are in wideband millimeter-wave systems.

Subharmonically pumped CMOS frequency conversion (up and down) circuits for 2-GHz WCDMA direct-conversion transceiver

This paper presents an 8-element linear phased array receiver in 0.18-mum SiGe BiCMOS technology for X-and Ku-band applications. The array receiver adopts RF phase shifting architecture and the active 4-bit phase shifter synthesizes a phase by adding two properly weighted I-and Q-input. With all the digital control circuitry, bandgap reference and ESD protection for all I/O pads, the receiver consumes 170 mA from a 3.3 V supply voltage. The receiver shows about 20 dB of power gain per channel at 12 GHz with a 3-dB gain bandwidth from 8.5 to 14.5 GHz. The rms gain error is less than 0.9 dB and the rms phase error is less than 6deg at 6-18 GHz for all the 4-bit phase states. The minimum NF is 3.85 dB at 10-11 GHz and typical input PldB at 12 GHz is -31 dBm. The overall chip size is 2.2times2.45 mm2. To our knowledge, this is the first demonstration of an RF-based phased array in a silicon chip with the record rms phase and gain errors at 6-18 GHz.