Kyeongsoon Cho

Design of area-efficient unified transform circuit for multi-standard video decoder

This paper proposes a method to perform the inverse transform operations for three popular video compression standards H.264, VC-1 and MPEG-4 using the concept of delta coefficent matrix. We designed the unified inverse transform circuit based on the proposed method. Our circuit supports 4-point and 8-point transforms for H.264, VC-1 and MPEG-4. The proposed unified circuit was verified on the SoC platform board synthesized into a gate-level circuit using 130nm standard cell library and showed its efficiency in terms of the area.

Circuit implementation for transform and quantization operations of H.264/MPEG-4/VC-1 video decoder

Current trend of digital convergence leads to the need of the video decoder that can support the multiple standards such as H.264, MPEG-4 and VC-1. We implemented a circuit to perform the transform and quantization operations for the three video compression standards. Instead of designing the circuit for each standard separately, we analyzed the transform and quantization operations in detail to find the possibilities of sharing resources such as adders and multipliers, and finally devised a common architecture that can be applied to all of them. The resultant circuit is efficient in terms of its size compared to the case of separate implementation for each standard.

Design of high-performance transform and quantization circuit for unified video CODEC

This paper presents the new high-performance circuit architecture of the transform and quantization for unified video CODEC. The proposed architecture can be applied to all kinds of transforms for the video compression standards such as JPEG, MPEG-1/2/4, H.264 and VC-1. It exploits the similarity of 4-point DCT and 8-point DCT using permutation matrices. Since our circuit accepts the transform coefficients from the users, it can be extended very easily to cover any kind of DCT-based transforms for future standards. The multipliers in the transform circuit are shared by the quantization circuit in order to minimize the circuit size. The quantization operations are performed using spare clock cycles during the transform operations in order to minimize the number of clock cycles required. We described the proposed transform circuit at RTL and verified its operation on FPGA board.

Design of Transform and Quantization Circuit for Multi-Standard Integrated Video Decoder

This paper presents a new method to design the circuit that can perform the inverse transform and inverse quantization operations for three popular video compression standards WMV9, MPEG-4 and H.264. We introduced a delta coefficient matrix and implemented the integrated inverse transform circuit based on the proposed idea. We designed the integrated inverse quantization circuit using a shared multiplier. The entire circuit was verified on the SoC platform board, synthesized into a gate-level circuit using 130nm standard cell library and showed its efficiency in terms of the circuit size.

Design of high-performance pedestrian and vehicle detection circuit using Haar-like features

This paper describes the design of high-performance pedestrian and vehicle detection circuit using Haar-like features for intelligent vehicle application. The proposed circuit uses a sliding window for every image frame in order to extract Haar-like features and to detect pedestrians and vehicles. A total of 200 Haar-like features per sliding window are extracted from Haar-like feature extraction circuit and the extracted features are provided to AdaBoost classifier circuit. In order to increase the processing speed, the proposed circuit adopts the parallel architecture and it can process two sliding windows at the same time. We described the proposed high-performance pedestrian and vehicle detection circuit using Verilog HDL and synthesized the gate-level circuit using 130nm standard cell library. The synthesized circuit consists of 1,388,260 gates and its maximum operating frequency is 203MHz. Since the proposed circuit processes about 47.8 640×480 image frames per second, it can be used to provide the real-time pedestrian and vehicles detection for intelligent vehicle application.

Implementation of an AMBA-Compliant IP for H.264 Transform and Quantization

This paper presents an AMBA-based IP to perform the forward and inverse transform and quantization required in the H.264 video compression standard. The transform and quantization circuit was optimized for area and performance. The AHB wrapper was added to the circuit for the AMBA-based operation. The user of the IP can specify how long the bus may be occupied by the IP and also where the video data are stored in the external memory. The AMBA-compliant operation of the proposed IP was verified on the platform board with Xilinx FPGA and ARM9 processor. We fabricated an MPW chip using 0.25mum standard cells to prove the correct operations on silicon

Trade-off between accuracy and speed for pedestrian detection using HOG feature

In order to detect pedestrians in many applications, histogram of oriented gradient (HOG) feature is widely used. Although HOG feature can provide high detection accuracy, fast detection time is hardly achieved due to its computational complexity. In this paper, a new method for pedestrian detection using HOG feature is proposed to achieve both high detection rate and fast detection time. Multi-scale cells and blocks of HOG feature are used to improve detection accuracy, and they are computed by using integral HOG to improve detection speed. In order to further improve detection quality in terms of accuracy and speed, two-stage approach is adopted in the proposed method. Experimental results show that the proposed method improves both detection rate and speed.

Design of AdaBoost classifier circuit using Haar-like features for automobile applications

This paper describes the design of AdaBoost classifier circuit using the Haar-like features for the automobile applications. In order to extract the features of an object, the proposed circuit uses the Haar-like feature extraction method. The proposed circuit extracts a total of 200 Haar-like features per sliding window. The extracted features are provided to the AdaBoost classifier circuit in order to determine whether the object is the expected one or not. A 48×96 or 64×64 sliding window with 10 window strides is used in the proposed circuit for the efficient pattern recognition. In order to increase the processing speed, the proposed circuit adopts the parallel architecture and it can process two sliding windows at the same time. We described the proposed high-performance pattern recognition circuit using Verilog HDL and synthesized the gate-level circuit using the 130nm standard cell library. The synthesized circuit consists of 428,397 gates and its maximum operating frequency is 203MHz. 148 240×8-bit, 107 192×10-bit, and one 200×102-bit SRAMs are used in the proposed circuit. The circuit processes 38.4 640×480 image frames per second, assuming ten different levels of resolution for each frame, i. e. nine successive scaling down for each 640×480 image frame.

An Efficient Architecture of High-Performance Deblocking Filter for H.264/AVC

We devised an efficient architecture of deblocking filter and implemented the circuit with 15,400 logic gates and a 160×32 dual-port SRAM using 0.25 μm standard cell technology. This circuit can process 88 image frames with 1,280 × 720 pixels per second at 166 MHz. Our circuit requires smaller number of accesses to the external memory than other approaches and hence causes less bus traffic in the SoC design platform.

Fast Calculation of Histogram of Oriented Gradient Feature by Removing Redundancy in Overlapping Block

In order to improve pedestrian detection accuracy, histogram of oriented gradient (HOG) feature is widely used in many applications. Although HOG feature can provide high detection accuracy, fast detection time is hardly achieved due to its computational complexity. Therefore, this paper describes a novel algorithm for fast calculation of HOG feature. In the proposed algorithm, HOG feature is calculated based on cells instead of overlapping blocks to avoid redundancy. Furthermore, by identifying key rules and sharing common operations in trilinear interpolation, the number of required operations in HOG feature calculation is reduced up to 60.5% while detection accuracy is not degraded at all. Therefore, the proposed method is applicable to many applications such as intelligent vehicles, robots, and surveillance systems in which both high detection rate and fast detection time are strongly required.