Kyoko Izuha

Using a highly accurate self-stop Cu-CMP model in the design flow

An accurate model for the self-stop copper chemical mechanical polishing (Cu-CMP) process has been developed using CMP modeling technology from Mentor Graphics. This technology was applied on data from Sony to create and optimize copper electroplating (ECD), Cu-CMP, and barrier metal polishing (BM-CMP) process models. These models take into account layout pattern dependency, long range diffusion and planarization effects, as well as microloading from local pattern density. The developed ECD model accurately predicted erosion and dishing over the entire range of width and space combinations present on the test chip. Then, the results of the ECD model were used as an initial structure to model the Cu-CMP step. Subsequently, the result of Cu-CMP was used for the BM-CMP model creation. The created model was successful in reproducing the measured data, including trends for a broad range of metal width and densities. Its robustness is demonstrated by the fact that it gives acceptable prediction of final copper thickness data although the calibration data included noise from line scan measurements. Accuracy of the Cu-CMP model has a great impact on the prediction results for BM-CMP. This is a critical feature for the modeling of high precision CMP such as self-stop Cu-CMP. Finally, the developed model could successfully extract planarity hotspots that helped identify potential problems in production chips before they were manufactured. The output thickness values of metal and dielectric can be used to drive layout enhancement tools and improve the accuracy of timing analysis.

Practical usage of simulation technology in CMP process development

In CMP process development for mass production of semiconductor devices, not only good planarity and uniformity but also compatibility with productivity such as defect reduction and cost performance is important. Exploiting the power of simulation technology is effective in such development, since it enables prediction of possible issues in advance so the total optimization of process integration and wiring design could be realized. In this presentation, two effective applications of simulations for CMP process development are addressed. First, an original Cu-CMP process model was developed on a commercially available CMP simulation tool of Mentor Graphics. This enables hotspot extraction from new designed product data [1]. Next, a simulation using finite element method (FEM) revealed that low-k delamination was caused by the local pressure concentration on the wafer. This issue was resolved by adopting a novel concept polishing pad which decreases the pressure concentration [2].