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Dive into the research topics where Kyoung Bong Rouh is active.

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Featured researches published by Kyoung Bong Rouh.


ION IMPLANTATION TECHNOLOGY 2012: Proceedings of the 19th International Conference on Ion Implantation Technology | 2012

Multi-wavelength Raman and photoluminescence characterization of implanted n+/p junctions under various rapid thermal annealing conditions

Woo Sik Yoo; Takeshi Ueda; Toshikazu Ishigaki; Kitaek Kang; Kyoung Bong Rouh; Yong Seok Eun; Choon Hwan Kim; Hyo Sang Kang

Arsenic (As+) implanted p-type wafers for n+ junction were prepared and annealed in a resistively heated, single wafer rapid thermal furnace in N2. The wafers were non-destructively characterized by multi-wavelength Raman spectroscopy and multi-wavelength photoluminescence (PL) spectroscopy before and after rapid thermal annealing (RTA). Sheet resistance and dopant profiles of n+/p junctions were measured using a four point probe and secondary ion mass spectroscopy (SIMS). Strong correlation among Raman, PL spectra, sheet resistance, dopant profile and RTA conditions were observed. Approximate dopant profiles, crystal quality, junction integrity, dopant activation/deactivation rates, and approximate profiles (location and density) of non-radiative recombination centers of As+ implanted wafers were successfully characterized by multi-wavelength Raman and PL measurements without making contact. Multi-wavelength Raman and PL can provide advantages as in-line, non-contact/non-destructive process and material ...


The Japan Society of Applied Physics | 2006

Novel threshold voltage fine control method for FETs within a wafer using LDSi (Locally Differentiated Scanning ion implant)

Kyoung Bong Rouh; Min Yong Lee; Seung Woo Jin; Yong Sun Sohn; Yong Soo Joung; Young Jong Ki; Il Keun Han; Yong Wook Song; sung wook Park

The novel threshold fine voltage (hereafter Vt) control method within a wafer was successfully developed. The locally differentiated scanning ion implant (hereafter LDSi) was developed in order to equalize Vt within a whole wafer. The wafer that was done by LDSi method showed very small Vt variation range of 117mV @ thin PMOS short channel (Vt range made by conventional implant without LDSi : 224mV). There was no long channel Vt shift. The portion of high speed DRAMs over 1GHz was increased from 47% to 84% by LDSi without IDD2 fail rate loss. Without decreasing of wafer per hour, we got the dramatic results.


Archive | 2010

Method of Fabricating Landing Plug in Semiconductor Device

Kyoung Bong Rouh


Archive | 2005

Method for manufacturing a cell transistor of a semiconductor memory device

Kyoung Bong Rouh; Seung Woo Jin; Min Young Lee


Archive | 2008

Non-uniform ion implantation apparatus and method thereof

Kyoung Bong Rouh; Seung Woo Jin; Min Yong Lee


Archive | 2007

Semiconductor device having a recessed gate and asymmetric dopant regions and method of manufacturing the same

Kyoung Bong Rouh; Seung Woo Jin; Min Yong Lee


Archive | 2005

Partial implantation method for semiconductor manufacturing

Kyoung Bong Rouh; Yong Sun Sohn; Min Yong Lee


Archive | 2007

Apparatus and method for thermally treating semiconductor device capable of preventing wafer from warping

Seung Woo Jin; Kyoung Bong Rouh


Archive | 2009

Recess Gate Type Transistor

Kyoung Bong Rouh; Seung Woo Jin; Min Yong Lee; Yong Soo Jung


Archive | 2008

METHOD FOR FABRICATING PMOS TRANSISTOR AND METHOD FOR FORMING DUAL GATE USING THE SAME

Kyoung Bong Rouh; Choon Hwan Kim; Il Cheol Rho

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