Kyriakos M. Deliparaschos

Evolution of autonomous and semi-autonomous robotic surgical systems: a review of the literature

Autonomous control of surgical robotic platforms may offer enhancements such as higher precision, intelligent manoeuvres, tissue‐damage avoidance, etc. Autonomous robotic systems in surgery are largely at the experimental level. However, they have also reached clinical application.

Fuzzy logic path tracking control for autonomous non-holonomic mobile robots: Design of System on a Chip

This paper presents a System on Chip (SoC) for the path following task of autonomous non-holonomic mobile robots. The SoC consists of a parameterized Digital Fuzzy Logic Controller (DFLC) core and a flow control algorithm that runs under the Xilinx Microblaze soft processor core. The fuzzy controller supports a fuzzy path tracking algorithm introduced by the authors. The FPGA board hosting the SoC was attached to an actual differential-drive Pioneer 3-DX8 robot, which was used in field experiments in order to assess the overall performance of the tracking scheme. Moreover, quantization problems and limitations imposed by the system configuration are also discussed.

A parameterised genetic algorithm IP core: FPGA design, implementation and performance evaluation

Genetic algorithm (GA) is a directed random search technique working on a population of solutions and is based on natural selection. However, its convergence to the optimum may be very slow for complex optimisation problems, especially when the GA is software-implemented, making it difficult to be used in real-time applications. In this article, a parameterised GA intellectual property core is designed and implemented on hardware, achieving impressive time-speedups when compared to its software version. The parameterisation stands for the number of population individuals and their bit resolution, the bit resolution of each individuals fitness, the number of elite genes in each generation, the crossover and mutation methods, the maximum number of generations, the mutation probability and its bit resolution. The proposed architecture is implemented in a field programmable gate array chip with the use of a very high-speed integrated-circuits hardware description language and advanced synthesis and place and route tools. The GA discussed in this work achieves a frequency rate of 92 MHz and is evaluated using the ‘travelling salesman problem’ as well as several benchmarking functions.

AI-Based Actuator/Sensor Fault Detection With Low Computational Cost for Industrial Applications

A low computational cost method is proposed for detecting actuator/sensor faults. Typical model-based fault detection (FD) units for multiple sensor faults require a bank of estimators [i.e., conventional Kalman estimators or artificial intelligence (AI)-based ones]. The proposed FD scheme uses an AI approach for developing of a low computational power FD unit abbreviated as iFD. In contrast to the bank-of-estimators approach, the proposed iFD unit employs a single estimator for multiple actuator/sensor FD. The efficacy of the proposed FD scheme is illustrated through a rigorous analysis of the results for a number of sensor fault scenarios on an electromagnetic suspension system.

A fast digital fuzzy logic controller: FPGA design and implementation

This paper describes an improved approach to design a Takagi-Sugeno zero-order type fast parameterized digital fuzzy logic controller (DFLC) processing only the active rules (rules that give a non-null contribution for a given input data set), at high frequency of operation, without significant increase in hardware complexity. To achieve this goal, an improved method of designing the fuzzy controller model is proposed that significantly reduces the time required to process the active rules and effectively increases the input data processing rate. The DFLC discussed in this paper achieves an internal core processing speed of at least 200 MHz, featuring two 8-bit inputs and one 12-bit output, with up to seven trapezoidal shape membership functions per input and a rule base of up to 49 rules. The proposed architecture was implemented in a field programmable gate array (FPGA) chip with the use of a very high-speed integrated-circuits hardware-description-language (VHDL) and advanced synthesis and place and route tools

A model-based embedded control hardware/software co-design approach for optimized sensor selection of industrial systems

In this work, a Field Programmable Gate Array (FPGA)-based embedded software platform coupled with a software-based plant, forming a Hardware-In-the-Loop (HIL), is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, and the nonlinear model of a maglev suspension. The physical process that represents the suspension plant is realized in a high-level system modeling environment, while the LQG controller is implemented on an FPGA. FPGAs allow to rapidly evaluate algorithms and test designs under real-world scenarios avoiding heavy time penalty associated with Hardware Description Language (HDL) simulators. Moreover, the HIL technique implemented shows a significant speed-up in the required execution time when compared to the software-based model.

FPGA–Based Efficient Hardware/Software Co–Design for Industrial Systems with Consideration of Output Selection

Abstract This work presents a field programmable gate array (FPGA)-based embedded software platform coupled with a software-based plant, forming a hardware-in-the-loop (HIL) that is used to validate a systematic sensor selection framework. The systematic sensor selection framework combines multi-objective optimization, linear-quadratic-Gaussian (LQG)-type control, and the nonlinear model of a maglev suspension. A robustness analysis of the closed-loop is followed (prior to implementation) supporting the appropriateness of the solution under parametric variation. The analysis also shows that quantization is robust under different controller gains. While the LQG controller is implemented on an FPGA, the physical process is realized in a high-level system modeling environment. FPGA technology enables rapid evaluation of the algorithms and test designs under realistic scenarios avoiding heavy time penalty associated with hardware description language (HDL) simulators. The HIL technique facilitates significant speed-up in the required execution time when compared to its software-based counterpart model.

On the use of fuzzy logic controllers to comply with virtualized application demands in the cloud

As virtualization technologies enable real-time CPU allocation, it is important to build controllers that adjust the allocation in a timely fashion avoiding resource saturation and hence, dissatisfaction of the end users of services. In this work, adaptive neuro-fuzzy inference, trained on Kalman and H∞ filters, has been used to adjust the CPU allocations based on observations of past utilization. When evaluating the performance of the proposed controller it is demonstrated that it provides even better performance than the filters it is trained on. In addition, there are no assumptions on the noise characteristics and due to the fact that the neuro-fuzzy controller can, in general, capture non-linear level processes, our controller is more robust than linear model based approaches, such as the Kalman and the H∞ filters.

On the issue of LQG embedded control realization in a Maglev system

Sensor selection in control design receives substantial interest in the last few years. We disseminate work on Field Programmable Gate Array (FPGA)-based embedded software platform validating a systematic sensor selection framework and target efficient FPGA resource allocation. Sensor selection combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, applied to a Maglev suspension. The nonlinear Maglev model is realized on software platform forming a Hardware-in-the-loop (HIL) as an economic and reliable validation platform for the design setup. The LQG controller was modeled in fixed point, described in Verilog Hardware Description Language (HDL) and tied up with an ethernet core to form an FPGA-in-the-loop system prior to logic synthesis and FPGA place and route. The results illustrate efficient FPGA resource allocation level pertinent to extending to a core sensor fault tolerant scheme.

Dynamic CPU resource provisioning in virtualized servers using maximum correntropy criterion Kalman filters

Virtualized servers have been the key for the efficient deployment of cloud applications. As the application demand increases, it is important to dynamically adjust the CPU allocation of each component in order to save resources for other applications and keep performance high, e.g., the client mean response time (mRT) should be kept below a Quality of Service (QoS) target. In this work, a new form of Kalman filter, called the Maximum Correntropy Criterion Kalman Filter (MCC-KF), has been used in order to predict, and hence, adjust the CPU allocations of each component while the RUBiS auction site workload changes randomly as the number of clients varies. MCC-KF has shown high performance when the noise is non-Gaussian, as it is the case in the CPU usage. Numerical evaluations compare our designed framework with other current state-of-the-art using real-data via the RUBiS benchmark website deployed on a prototype Xen-virtualized cluster.