Kyu-Ha Shim

Enabling Solutions for 28 nm CMOS Advanced Junction Formation

Controlling short channel effects for further scaled CMOS is required to take full advantage of the introduction of high K/metal gate or stress induced carrier mobility enhancement. Ultra‐Shallow junction formation is necessary to minimize the short channel effects. In this paper, we will discuss the challenges for 28 nm Ultra‐Shallow Junction formations in terms of figure of merits of Rs/Xj and junction leakage. We will demonstrate that by adopting and integrating Carborane (CBH, C2B10H12) molecular implant and Phosphorus along with co‐implantation and PTC II (VSEA Process Temperature Control) technology, sub‐32 nm pLDD and nLDD junction targets can be timely achieved using traditional anneals. Those damage engineering solutions can be readily implemented on state‐of‐the‐art 28 nm device manufacturing.

28nm Device improvement studies by replacing Indium with Gallium halo

Optimization of halo profile for advanced MOSFET device is known to be very critical and challenging. Halo profiles around channel can cause carrier mobility degradation, leakage and higher Vt mismatch. Indium and high scattering P-type dopant (HS-P) mixed halo formation have been used widely for n-FET devices. Gallium has a better activation than Indium and is heavier specie than HS-P. Gallium could be promising specie for device improvement through halo optimization in planar devices or ground plane/retrograde well for better FinFET leakage characteristics. In this paper, Gallium is used to replace Indium halo on bare and device wafers using a poly-SiON 28nm process. Secondary Ion Mass Spectroscopy (SIMS) was employed for dopant profiles after anneals. Device gain in drive current with better Drain Induced Barrier Lowering or DIBL by 12mV was observed when Gallium replaced Indium in the HS-P/Indium mixed halo. The observed excessive device shift when Gallium was used to replace HS-P halo will be discussed in a future study. Ga for halo formation is not an plug/play and the interaction among the co-implant and dopant through implant induced damage should be investigated in the integration flow.

Process Transferability from a Spot Beam to a Ribbon Beam Implanter: CMOS Device Matching

The exercise of dose and energy matching is the standard way to integrate a new implanter into a manufacturing fab. Sheet resistance and secondary‐ion mass spectroscopy (SIMS) measurements on bare silicon wafers have been the conventional metrologies to establish dose/energy equivalence between implanters. Invariably, matched performance on bare silicon wafers translated into matched device performance between implanters of the same kind. However, as devices scale down to 90 run and beyond, the implanter design can become a significant factor in terms of process matching. In this paper we discuss the dynamics of transferring 120–90nm logic processes from a traditional batch, spot beam implanter to a single wafer (SW), parallel ribbon beam implanter. The results show that the traditional approach to dose matching involving the basic parameters of specie, dose and energy, although necessary, is inadequate to provide matched device performance between the two implanter types. 3‐dimensional effects which cann...

High Current Implant Precision Requirements for Sub‐65 nm Logic Devices

As CMOS devices shrink they become increasingly sensitive to variations of ion beam angular properties and beam current density. In sub‐65 nm devices beam divergence and beam steering variations at levels commonly seen in high current implanters for Source/Drain Extension (SDE) implants could significantly shift device characteristics compromising yield and robustness of manufacturing process. In this paper we review the implant precision requirements for Source/Drain Extension (SDE) formation for sub‐65nm node devices. TCAD simulation was used to analyze the effects of beam divergence and steering errors for an on‐axis (0°) SDE implant on sub‐65 nm NMOS HP devices. Effects of energy contamination introduced along with decelerated low energy ions in p‐type SDE implants in PMOS devices is also discussed. Response of device electrical characteristics to variation of beam angle properties is quantified and beam angle control requirements for state‐of‐the‐art ultra‐low energy implanters formulated.

Impact of gallium implant for advanced CMOS halo/pocket optimization

Optimization of halo profile for advanced MOSFET device is important to control device short channel effect as well as device leakage. Multiple halo implants, such as mixture of Indium and boron to tailor the halo formation, have been used widely for n-FET devices. Amid its AMU and solubility, Gallium has a potential for better halo activation than Indium and reduced lateral straggling than boron. Therefore, Gallium could be a promising specie for device improvement through 1) halo optimization in planar devices, or 2) ground plane for retrograde well for better FinFET leakage characteristics. In this paper, Gallium is used to replace high scattering P dopant (HS-P) halo for SRAM or HS-P cluster halo for core NFET using a poly-SiON 28nm process with bare wafers and device splits. Secondary Ion Mass Spectroscopy (SIMS) was employed for dopant profiles for as-implanted and after thermal process. It is shown that when replacing HS-P or HS-P cluster halo by Gallium an excessive device shift is observed. The overlap capacitance indicates that overlap lateral diffusion regions are significant different with Gallium halo than established process flow. The paper will discuss potential underlying physical mechanisms.

“Abnormal” angle response curves of TW/Rs for near zero tilt and high tilt channeling implants

Angle control has been widely accepted as the key requirement for ion implantation in semiconductor device processing. From an ion implanter point of view, the incident ion direction should be measured and corrected by suitable techniques, such as XP-VPS for the VIISta implanter platform, to ensure precision ion placement in device structures. So called V-curves have been adopted to generate the wafer-based calibration using channeling effects as the Si lattice steer ions into a channeling direction. Thermal Wave (TW) or sheet resistance (Rs) can be used to determine the minimum of the angle response curve. Normally it is expected that the TW and Rs have their respective minima at identical angles. However, the TW and Rs response to the angle variations does depend on factors such as implant species, dose, and wafer temperature. Implant damage accumulation effects have to be considered for data interpretation especially for some “abnormal” V-curve data. In this paper we will discuss some observed “abnorma...

Mitigating eSiGe strain relaxation using cryo-implantation technology for PSD formation

Strain techniques have been adopted and widely used in the advanced nodes since early 65nm for carrier mobility improvement. For PMOS, eSiGe incorporation in the SD is the process of choice to induce compressive strain in the channel for mobility improvement. To further lower the contact resistance, it is preferred to boost Boron concentration for pSD formed by eSiGe process. Normal implant process could lead strain relaxation caused by implant damage. In this paper, cryo-implantation technology is applied and characterization of strain relaxation is conducted using a state-of-the-art 28nm CMOS process flow. Experimental results indicate strain relaxation can be reduced with cryo implants relative to the room temperature implants. This study clearly showed that cryo-implantion reduced damage formation resulting in junction leakage reduction.

Impact of Dose Rate Effects and Damage Engineering on Device Performance

Traditional implant conditions during source/drain formation process, such as dopant, dose, energy and incident angle have been known as key parameters determining device electrical characteristics. As devices scale down, instant dose rate of BF2 ion implantation, however, should be considered as an important factor to control buried channel PMOS characteristics since fluorine and boron diffusion behavior can be varied depending on implant damage and results in change of effective channel length. Ribbon beam single wafer high current implanters enable ion beam density to be modulated. By changing beam size with same beam current during source/drain implantation, PMOS electrical characteristics of 70nm Flash memory have been investigated. With achieved results, device matching to spot beam batch ion implanter has been demonstrated.

Epi process margin improvement using co-implantation to control Phosphorus diffusion in a DRAM manufacturing

Co-implantation has been proven to be an effective method to reduce Transient Enhanced Diffusion (TED). In this paper, the effect of Carbon co-implant energy, dose, and combined with Fluorine implants were investigated to control TED for a contact Phosphorus. With optimized co-implant conditions, Dynamic Random Access Memory (DRAM) device wafers were used to verify that the Epi process window can be enlarged due to better control of Phosphorus TED. The study revealed that Carbon suppresses the Phosphorus diffusion tailing and reduces Gate Induced Drain Leakage (GIDL) without degrading Vt and contact resistance performances. With the reduction of Phosphorus diffusion and GIDL, thinner selective Epi layer can be tolerated, resulting in widened process window of Epi final thickness and increased selective Epi process margin.

vMask® Usage in Semiconductor Foundry Manufacturing

Time and cost of development are key factors for the success of advanced devices. Device development requires multiple iterations of carefully designed implant splits to optimize device performance and yield. Conventional whole wafer implant splits are both time consuming and costly, due in part to the need to gain adequate statistics with the relatively high wafer to wafer variability of early stage development devices. VMASK, which provides multiple implant conditions on a single wafer, can be applied for a variety of corner splits, such as well, halo, and LDD implants to achieve target device performance and optimize process flow. By reducing the impact of variability from other process steps and the direct reduction in the number of device wafers required by a factor of four, a significant reduction in both wafer cost and cycle time can be achieved. In this paper, the benefits of VMASK were discussed and evaluated in a high volume production foundry fab and applied in the process development.