Kyu-hyoun Kim

Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems

Recent DRAM specifications exhibit increasing refresh latencies. A refresh command blocks a full rank, decreasing available parallelism in the memory subsystem significantly, thus decreasing performance. Fine Granularity Refresh (FGR) is a feature recently announced as part of JEDECs DDR4 DRAM specification that attempts to tackle this problem by creating a range of refresh options that provide a trade-off between refresh latency and frequency. In this paper, we first conduct an analysis of DDR4 DRAMs FGR feature, and show that there is no one-size-fits-all option across a variety of applications. We then present Adaptive Refresh (AR), a simple yet effective mechanism that dynamically chooses the best FGR mode for each application and phase within the application. When looking at the refresh problem more closely, we identify in high-density DRAM systems a phenomenon that we call command queue seizure, whereby the memory controllers command queue seizes up temporarily because it is full with commands to a rank that is being refreshed. To attack this problem, we propose two complementary mechanisms called Delayed Command Expansion (DCE) and Preemptive Command Drain (PCD). Our results show that AR does exploit DDR4s FGR effectively. However, once our proposed DCE and PCD mechanisms are added, DDR4s FGR becomes redundant in most cases, except in a few highly memory-sensitive applications, where the use of AR does provide some additional benefit. In all, our simulations show that the proposed mechanisms yield 8% (14%) mean speedup with respect to traditional refresh, at normal (extended) DRAM operating temperatures, for a set of diverse parallel applications.

A 512-mb DDR3 SDRAM prototype with C/sub IO/ minimization and self-calibration techniques

A 1.5-V 512-Mb DDR3 Synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C IO minimization, which were achieved by on-die-termination (ODT)-merged output drivers, SCR type ESD protection, and self-calibration scheme. The hybrid latency control scheme can turn the DLL off in standby mode, reducing power consumption. User-friendly functions such as temperature read-out from on-chip sensor and per-bank-refresh were also implemented.

A 20-gb/s 256-mb DRAM with an inductorless quadrature PLL and a cascaded pre-emphasis transmitter

A 20GB/s 1.8V 256MB DRAM is designed and fabricated using an 80nm CMOS process. An inductorless tetrahedral oscillator generates inherent quadrant phases combined with a cascaded pre-emphasis transmitter to achieve a 10Gbit/s/pin data rate.

An 8-bit-resolution, 360-/spl mu/s write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)

This fast accurate nonvolatile analog memory (NVAM) cell is based on EEPROMs. Programming rate is constant using a single program pulse, enhancing programming speed and accuracy. A prototype chip containing 8/spl times/128 9/spl times/13.6 /spl mu/m/sup 2/ NVAM cells uses 0.8 /spl mu/m 2-poly CMOS. Each cell stores more than 8 b levels in 360 /spl mu/s.

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator

In this paper, a wide frequency open-loop quadrature generator is sufficiently compact to allow many stages to be cascaded affordably. The generator is built from cascaded quad corrector stages, each of which in turn, can be understood as a modification of a common interpolating 4-stage ring oscillator. In the circuit, the delay of each stage is a linear superposition of the delays Phi of the associated inner and outer loop elements. If the outer loop element inputs are made independent, the driven oscillator is resulted. Provided the input drive is sufficient, the frequency of the driven oscillator is that of the driving input, and the phase of each internal node is an interpolation of the phase of its input drive and the phase of the preceding stage. This interpolation acts to average offsets from quadrature in the incoming phases. If the input drive is insufficient, the oscillator will run near its natural or unloaded frequency, omega0=2pifo.

A 1.4 Gb/s DLL using 2nd order charge-pump scheme with low phase/duty error for high-speed DRAM application

A technique for reducing the phase error of DLL/PLLs, due to non-ideal characteristics of the charge pump, is proposed. It makes the output of the charge pump virtually grounded, to eliminate the current mismatch and to seamlessly convert the locking information into digital form. A DLL is designed and fabricated to exhibit duty-cycle corrector performance with a speed of 1.4 Gb/s.

Built-in duty cycle corrector using coded phase blending scheme for DDR/DDR2 synchronous DRAM Application

This paper describes DLL (delay locked loop) with built-in DCC (duty cycle correction) capability using a newly proposed coded phase blending scheme. The proposed scheme dramatically improves the DCC range and also enhances the total DLL performance. The DLL has been designed and fabricated within 1G-bit DDR (double data rate) synchronous DRAM using 0.11 /spl mu/m process and the measurement data show that it has unlimited DCC range, faster turn-on speed and smaller jitter compared with our previous work (2001).

An 8 Gb/s/pin 9.6 ns Row-Cycle 288 Mb Deca-Data Rate SDRAM With an I/O Error Detection Scheme

This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with original data seamlessly without a timing bubble. A 288 Mb SDRAM has been designed using the proposed scheme combined with fast cycling core techniques to have both high I/O bandwidth and fast random cycling. Measured results show that the chip exhibits per-pin data rate of 8 Gb/s and row cycle time of 9.6 ns

Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

DLL and improved I/O circuits are for 500 Mb/s/pin DDR SDRAM. This digitally-controlled DLL has inherent duty cycle correction capability, enabling fast re-locking upon standby-mode exit. Data input circuits, such as internal delay control and digital sense amplifier, reduce setup/hold window to 0.3 ns. The output data driver has 62% decreased pattern-dependent skew.

DOE Advanced Scientific Computing Advisory Subcommittee (ASCAC) Report: Top Ten Exascale Research Challenges

Exascale computing systems are essential for the scientific fields that will transform the 21st century global economy, including energy, biotechnology, nanotechnology, and materials science. Progress in these fields is predicated on the ability to perform advanced scientific and engineering simulations, and analyze the deluge of data. On July 29, 2013, ASCAC was charged by Patricia Dehmer, the Acting Director of the Office of Science, to assemble a subcommittee to provide advice on exascale computing. This subcommittee was directed to return a list of no more than ten technical approaches (hardware and software) that will enable the development of a system that achieves the Departments goals for exascale computing. Numerous reports over the past few years have documented the technical challenges and the non¬-viability of simply scaling existing computer designs to reach exascale. The technical challenges revolve around energy consumption, memory performance, resilience, extreme concurrency, and big data. Drawing from these reports and more recent experience, this ASCAC subcommittee has identified the top ten computing technology advancements that are critical to making a capable, economically viable, exascale system.