Kyu Sik Cho

COPLANAR AMORPHOUS SILICON THIN FILM TRANSISTOR FABRICATED BY INDUCTIVELY COUPLED PLASMA CHEMICAL VAPOR DEPOSITION

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively coupled plasma (ICP) chemical vapor deposition (CVD) have been investigated. The ICP-CVD a-Si:H films deposited at the pressure of 30 mTorr exhibited the hydrogen content of 17 at. %, a photosensitivity of 106 at 100 mW/cm2 and a conductivity activation energy of 0.9 eV. A novel coplanar self-aligned a-Si:H thin film transistor was fabricated using Ni-silicide gate and source/drain electrodes. The simultaneous Ni-silicide formation of gate and source/drain regions using the stacked layers of thin a-Si:H, silicon nitride (SiNx) and a-Si:H reduces the offset length between gate and source/drain, which leads to the coplanar a-Si:H thin film transistor (TFT). This self-aligned a-Si:H TFT exhibited a field effect mobility of 0.44 cm2/V s, threshold voltage of 5.3 V and subthreshold slope of 0.5 V/dec. The coplanar geometry reduces the parasitic capacitance and parasitic resistance compared with t...

Hydrogenated amorphous silicon thin-film transistor with a thin gate insulator

Thinning the gate insulator in an hydrogenated amorphous silicon thin-film transistor (a-Si:H TFT) has been studied in a coplanar structure. The threshold voltage decreases with decreasing gate insulator thickness without changing the field effect mobility significantly. The reduction in the threshold voltage is due to the decrease in the charge traps in the SiN/sub x/ and in its film thickness. The coplanar a-Si:H TFT with a gate insulator thickness of 35 nm exhibited a field effect mobility of 0.45 cm/sup 2//Vs and a threshold voltage of 1.5 V. The thickness of the gate insulator can be decreased in the coplanar a-Si:H TFTs because of the planarized gate insulator.

Coplanar amorphous silicon thin film transistor fabricated by inductively-coupled plasma CVD

Abstract The electrical and optical properties of the a-Si:H films deposited by inductively-coupled plasma chemical vapour deposition (ICP-CVD) have been investigated. The ICP-CVD a-Si:H films deposited at 30 mTorr exhibited the deposition rate of 0.9 A/s and the hydrogen content of 17 at.%. A novel coplanar self-aligned a-Si:H thin film transistor has been fabricated using Ni-silicide gate and source/drain contacts. The coplanar a-Si:H TFT exhibited a field effect mobility of 0.6 cm 2 /Vs, a threshold voltage of 2.3 V, a subthreshold slope of 0.5 V/dec.

Copper gate hydrogenated amorphous silicon TFT with thin buffer layers

We demonstrated a Cu gate hydrogenated amorphous silicon thin-film transistor (TFT) with buffer layers. We introduced an AlN/Cu/Al/sub 2/O/sub 3/ multilayer for a gate of an a-Si:H TFT. The Al/sub 2/O/sub 3/ improves the adhesion to glass substrate and AlN protect the Cu diffusion to the TFT and plasma damage to Cu during plasma enhanced chemical vapor deposition of silicon-nitride. An a-Si:H TFT with a Cu gate exhibited a field effect mobility of 1.18 cm/sup 2/ V/s, a gate voltage swing of 0.87 V/dec., and a threshold voltage of 3.5 V.

A novel coplanar amorphous silicon thin-film transistor using silicide layers

A novel, coplanar, hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) was fabricated by depositing a triple layer consisting of a-Si:H, silicon-nitride, and a-Si:H. After patterning the top two layers in the gate stack, the devices were doped and a 30 nm Ni layer was deposited. The devices were then annealed for 1 h at 230/spl deg/C to form self-aligned, low resistive Ni-silicide. The fabricated coplanar a-Si:H TFT exhibits a field effect mobility of 0.6 cm/sup 2//Vs, a threshold voltage of 2 V, a subthreshold slope of 0.4 V/dec, and an on/off current ratio of /spl sim/10/sup 7/.

Performance improvement of polycrystalline thin-film transistor by adopting a very thin amorphous silicon buffer

A novel polycrystalline thin-film transistor (TFT) with a very thin (<10 nm) a-Si:H buffer has been studied. The off-state leakage current of the coplanar polycrystalline silicon (poly-Si) TFT was reduced using quadruple layers of a-Si:H, SiNx, thinner a-Si:H and poly-Si and by simultaneous silicide formation of the source, drain and gate contacts. While offset-gate and lightly doped drain (LDD) poly-Si TFT structures require additional mask steps to form the field-reduced regions, the proposed poly-Si TFT needs only 2 photo-mask steps. The on–off current ratio increases from 106 to 108 by adopting a thinner a-Si:H buffer on the poly-Si.

12.2: Large-Area Poly-Si on Glass by UV Scan Heating

The amorphous silicon (a-Si)over 300 × 350 mm2 could be completely crystallized by using silicide mediated crystallization (SMC)of a-Si by means of UV scan heating. A-Si having a 2.0 × 1013 atoms/cm2 Ni area density was crystallized in 10 minutes without having amorphous phase inside and the grain size was ∼20 μm. The field effect mobilities and threshold voltages of the p-channel poly-Si TFTs were 35 ∼ 40 cm2/Vs and 0.6 ∼ 0.7 V/dec, respectively, over 300 × 350 mm2.

P‐4: SPC Poly‐Si TFT Having a Maximum Process Temperature of 380°C

A very thin Ni layer was deposited onto a-Si, which was annealed for crystallization in the presence of the electric field. The NiSi2 precipitates were formed at the a-Si surface, and needle-like crystallites have ben found in the a-Si network even at 350°C. The poly-Si crystallized at 380°C has been used for the TFT, exhibiting a field effect mobility of 51 cm2/Vs and a threshold voltage of −2.2 V.

A polycrystalline silicon thin-film transistor with a thin amorphous buffer

We have developed a novel, low off-state leakage current polycrystalline silicon (poly-Si) thin-film transistor (TFT) by introducing a very thin hydrogenated amorphous silicon (a-Si:H) buffer on the poly-Si active layer. The a-Si:H buffer is formed on the whole poly-Si and thus no additional mask step is needed. With an a-Si:H buffer on poly-Si, the off-state leakage current of a coplanar TFT is remarkably reduced, while the reduction of the on-state current is relatively small. The poly-Si TFT with an a-Si:H buffer exhibited a field effect mobility of 12 cm/sup 2//Vs and an off-state leakage current of 3 fA//spl mu/m at the drain voltage of 1 V and the gate voltage of -5 V.

An amorphous silicon triode rectifier switching device for active-matrix liquid-crystal display

A triode rectifier switching (TRS) device composed of two amorphous silicon (a-Si) diodes and one resistor has been demonstrated experimentally to be a good switching device for active-matrix liquid-crystal display (AMLCD). The output and transfer characteristics of a TRS are very similar to those of an a-Si thin-film transistor. High on/off current ratio (>5/spl times/10/sup 6/) and low off-state leakage currents (<0.4 pA) have been demonstrated with a-Si diodes and a-Si resistor, indicating that the TRS is suitable for high-performance switching devices for AMLCD.