Kyung Ki Kim

On-Chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits

Accurate performance-degradation monitoring of nanometer MOSFET digital circuits is one of the most critical issues in adaptive design techniques for overcoming the performance degradation due to aging phenomena such as negative bias temperature instability (NBTI) and hot carrier injection (HCI). Therefore, this paper proposes new on-chip aging sensor circuits which deploy a threshold voltage detector for monitoring the performance degradation of an aged MOSFET. The new aging sensor circuits measure the threshold voltage difference between a NBTI/HCI stressed MOSFET device and a NBTI/HCI unstressed MOSFET device using an inverter chain and a phase comparator and digitalize the phase difference induced by the threshold voltage difference. The proposed sensor circuits achieve a direct correlation between the threshold voltage degradation and the phase difference (a phase difference resolution of 1 ns per 0.01 V threshold voltage shift). Also, the circuits are almost independent of temperature variation due to symmetrical circuit structures. A 45 nm CMOS technology and predictive NBTI/HCI models have been used to implement and evaluate the proposed circuits. The implemented layout size is 18.58 x 7.97 μm2; the post-layout power consumption is 18.57 μW during NBTI/HCI stress mode and 30.86 μW during NBTI/HCI measurement mode on average.

Correlation between the Activities of Daily Living of Stroke Patients in a Community Setting and Their Quality of Life.

[Purpose] The present study aimed to determine the correlation between the activities of daily living and the quality of life (QOL) of patients with chronic stroke. [Subjects and Methods] The study subjects were 68 patients with stroke. Three questionnaires were distributed by visiting the subjects. [Results] All the items and total scores of the functional independence measure (FIM) showed a high correlation with the QOL total score. The relationship between the activities of daily living and the total QOL score showed a significant positive correlation. Among the FIM items, mobility and social cognition showed the most significant effects. The modified r2 value was 0.67, mobility and social cognition explained approximately 67% of the change in the QOL. [Conclusion] The activities of daily living of the patients with chronic stroke and their QOL showed a high correlation. Among the FIM items, mobility (transfers) and social cognition had the largest effects on the total QOL score.

Ultralow-Voltage Power Gating Structure Using Low Threshold Voltage

A novel power gating (PG) structure using only low-threshold-voltage metal-oxide-semiconductor field-effect transistors (MOSFETs) is proposed to extend the PG to an ultralow-voltage region ( ~ 0.3 V). The proposed structure deploys series-connected low-V th footers with two virtual ground ports and selectively chooses the logic cells for connecting them to each virtual ground port according to the delay criticality. Furthermore, additional circuitry is designed to reduce not only the subthreshold leakage current but also the gate-tunneling leakage and to reduce the wake-up time and rush current compared to the conventional PG. The total PG switch size of the proposed PG structure including the additional circuits is less than the conventional one. The simulation results are compared to those of other well-known circuit schemes and show that, in the ultralow-voltage region, the other high-V th-based PG schemes cannot be used due to the impractical delay increase and long wake-up time, whereas the proposed PG structure keeps the balance among the critical PG issues. The proposed PG is evaluated using inverter chains and ISCAS85 benchmark circuits at 0.6-V supply voltage, which are designed using 45-nm complementary metal-oxide-semiconductor predictive technology model.

Optimal Body Biasing for Minimum Leakage Power in Standby Mode

This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, the control system determines the optimal trade-off between supply voltage and the forward body bias voltage to satisfy the performance requirement. In the standby mode, a new optimal body-bias technique in nanoscale CMOS technology is implemented to monitor subthreshold, gate tunneling, and band-to-band tunneling leakage current and reduce leakage current by optimal substrate bias voltage(forward of reverse biasing). The optimal body bias control system reduces the leakage current by up to 1000 times for ISCAS85 benchmark circuits designed using 32nm CMOS technology

On the modeling and analysis of jitter in ATE using Matlab

This paper presents a new jitter component analysis method for mixed mode VLSI chip testing in automatic test equipment (ATE). The separate components are analyzed individually and then combined using Matlab. The Matlab simulation shows how jitter components combine and how the total jitter depends on the jitter injection sequence. The relationship among jitter components is presented and the superposition of the jitter components is verified. This new technique gives test engineers an insight into how the jitter components interact.

Hybrid CMOS and CNFET Power Gating in Ultralow Voltage Design

This paper proposes a new hybrid MOSFET/carbon nanotube FET (CNFET) power-gating (PG) method using 32 nm technology in the ultralow-voltage region (~0.4 V). Traditionally, PG is one of the most effective methods to reduce the power dissipation of systems in sleep mode, but it suffers from increased propagation delay and wake-up time due to the high-threshold voltage of power switches in the low-voltage region. In this paper, to reduce the propagation delay and wake-up time of the PG structure while keeping low leakage power in the sleep mode, the CNFET power switches are combined with silicon MOSFET logic cells. The proposed hybrid structure reduces the time gap in switching over from silicon MOSFET to CNFET technology. For the tradeoff between wake-up overhead and leakage power saving, a new four-power-mode PG structure and a new two-pass PG structure using back-gate biasing of the CNFET switches are used. The simulation results of the proposed hybrid PG at 0.4 V are compared with those of the logic blocks without PG and the MOSFET PG structure using low-threshold voltage power switches. The simulation results show that the proposed hybrid structure reduces the total leakage power by 69.07%, the rush current by 5.13%, and the delay by 5.96%, on average, compared to the conventional PG structure for ISCAS85 benchmark circuits designed in 32 nm technology. More specifically, the proposed structure reduces the total leakage by 95.85% at the cost of 3% delay penalty compared to the logic blocks without PG for ISCAS85 benchmark circuits designed in 32 nm technology.

Analysis and Simulation of Jitter Sequences for Testing Serial Data Channels

This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The primary goal is the generation of a signal containing a known amount of each jitter component. This signal can then be used for testing high speed serial data channels. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining them are modeled, simulated and evaluated. Model simulation using Matlab is utilized to show the unique features of the components when they are combined into different injection sequences for producing the total jitter. Sequence dependency is investigated in depth and the validity of superposition of jitter components for typical values is confirmed. A good agreement between theory and simulation is verified; these results allow test engineers to have an insight into the interactions among jitter components in serial data channels.

Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits

Abstract —In deeply scaled CMOS technologies, two major non-ideal factors are threatening the survival of the CMOS; i) PVT (process, voltage, and temperature) variations and ii) leakage power consumption. In this paper, we propose a novel post-silicon tuning methodology to scale optimum voltage and frequency “dynamically”. The proposed design technique will use our PVT sensor circuits to monitor the variations and based on the monitored variation data, voltage and frequency will be compensated “automatically”. During the compensation process, supply voltage is dynamically adjusted to guarantee the minimum total power consumption without violating the frequency requirement. The simulation results show that the proposed technique can reduce the total power by 85% and the static power by 53% on average for the selected ISCAS’85 benchmark circuits with 45 nm CMOS technology compared to the results of the traditional PVT compensation method. Keywords —PVT Variation sensors, Yield, Voltage Scaling, Frequency Scaling

Ultra-low voltage high-speed Schmitt trigger circuit in SOI MOSFET technology

This paper proposes a novel ultra-low voltage and high speed Schmitt trigger circuit designed in silicon-on-insulator (SOI) technology. The proposed circuit is designed using dynamic threshold MOS (DTMOS) technique and multi-threshold voltage CMOS (MT-CMOS) technique to reduce power consumption and accomplish high speed operation. The experiment shows the proposed Schmitt trigger circuit consumes 4.68µW at 0.7V power supply voltage and the circuit demonstrates the maximum switching speed of 170psec.

Analysis of time dependent dielectric breakdown in nanoscale CMOS circuits

As CMOS technology is scaled down more aggressively; the reliability mechanism (or aging effect) caused by progressive gate oxide breakdown, also called time dependent dielectric breakdown (TDDB), has become a major reliability concern. With the present of TDDB, it is difficult to control the ON current of the MOSFET device. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the TDDB effects on delay and power of the nanoscale CMOS circuits are analyzed using inverter chains and ISCAS85 benchmark circuits, which are designed using 45-nm CMOS predictive technology model. Finally, we discuss post-silicon adaptive tuning techniques to compensate the TDDB impact on the CMOS circuits.