Kyung-Wook Shin

A Multi-mode LDPC Decoder for IEEE 802.16e Mobile WiMAX

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a 0.18- uf06dm CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V

An efficient implementation of SHA processor including three hash algorithms (SHA-512, SHA-512/224, SHA-512/256)

This paper describes a design of SHA processor implementing three hash algorithms of SHA-512, SHA-512/224 and SHA-512/256. The SHA processor generates digests of three different lengths with 512, 224, and 256 bits according to hash algorithms. It was designed that the initial hash values of SHA-512/224 and SHA-512/256 were generated using SHA-512 and it was based on 32-bit datapath, resulting in an area-efficient implementation. The SHA processor designed with HDL was verified by FPGA implementation. The SHA processor synthesized with 0.18ßm CMOS cell library occupies 27,368 gate equivalents (GEs) and can operate up to 185 MHz clock frequency. The SHA processor can be used for IoT security applications.