Kyungsu Park

Controlled Wafer Release in Clustered Photolithography Tools: Flexible Flow Line Job Release Scheduling and an LMOLP Heuristic

As a clustered photolithography tool (CPT) in semiconductor wafer manufacturing can cost as much as US

Performance models for dual-arm cluster tools

100 million, it must be operated efficiently. To maximize throughput, wafers are generally admitted to a CPT opportunistically, that is, as soon as they are available and the tool can accept them. Here, our goal is to develop release methods that retain throughput but increase manufacturing agility. As Petri net methods prove intractable, we develop a heuristic based on the use of flexible flow line models for the CPT. Such models are appropriate when the tool throughput for each class of wafers is dictated by the bottleneck process time plus unavoidable robot handling overhead. The heart of the heuristic is a lexicographic multiple objective linear program (LMOLP). It first ensures that wafers exit the tool as early as possible and subsequently delays the wafer admission to minimize the mean residency time.

Control of wafer release in multi cluster tools

Cluster tools with a dual-arm wafer transport robot are common in semiconductor wafer manufacturing. However, existing modeling methods suffer either from computational complexity (e.g., Petri nets, detailed simulation) and the resulting dearth of insight or from simplicity and its attendant loss of accuracy and expression (e.g., Ax+B models). Looking toward application in tool configuration optimization, performance evaluation and fab-wide simulation models, we develop expressive and computationally tractable equations and recursions for the cycle time of such cluster tools. The models include transient periods and robot behavior to express nonlinearities in tool performance. The models incorporate the affinity of such tools toward lots with certain numbers of wafers. We conduct simulations of dual-arm cluster tools to assess the quality of our models and compare performance and computational complexity between various approximation methods.

Performance evaluation of deterministic flow lines: Redundant modules and application to semiconductor manufacturing equipment

Due to the impending transition to 450 mm diameter wafers and efforts toward customization, an increase in setups and transient operation is anticipated for multi cluster tools in semiconductor wafer manufacturing. Clustered photolithography tools are a key class of tools facing this future. Two primary performance metrics that will be used to assess the implications of these changes are throughput and yield. This paper proposes optimization algorithms for wafer release control, which seek to improve yield by minimizing the residency time of wafers in a tool, while maintaining the maximum throughput. We also suggest heuristic algorithms to control the system in transient state. These algorithms address both transient and steady state behavior in a flow line relaxation of the system. The controls are intended to provide guidance for lower level robot controllers.

Models of Clustered Photolithography Tools for Fab-Level Simulation: From Affine to Flow Line

Fab level simulation is often used to evaluate the performance of control policies, capacity changes, mix/volume changes and design decisions in semiconductor wafer manufacture. As cluster and multi-cluster tools, such as the linked photolithography tool, are of increasing prominence in semiconductor wafer manufacture, it is important to have expressive and efficient models of these tools for use in fab-level simulation. Existing models are either too detailed for practical use or do not include key features such as the nonlinearity of tool cycle time as a function of the number of wafers per lot. To address these issues, we develop theory for the wafer exit time from a flow line with parallel servers at each process and extend it for practical application. We use the max-plus algebra to obtain an upper bound for the wafer completion times which requires less computation than full flow line simulation. We conjecture that the bound is exact; all cases studied show this to be true. Our conjectured exit time expression is independent of the order of the servers. We use our expression to develop equipment models for fab level simulation. We conduct numerical experiments that show the models are computationally efficient.

Cluster tool design comparisons via simulation

Fab-level discrete-event simulation is an important practical tool for the analysis and optimization of semiconductor wafer fabricators. In such facilities, a clustered photolithography tool (CPT) is by far the most expensive tool and often the capacity bottleneck. In this paper, we consider linear, affine, flow line, and detailed models of CPTs for use in fab-level simulation. We develop extensions to affine and flow line models and demonstrate exactly how to convert raw CPT data into the various models. Using a detailed CPT model based on industry data as the baseline, numerical experiments are conducted to test the models’ fidelity for cycle time, lot residency time, and throughput. We also compare the computational burden of each model class. Further simulations are conducted to test the models’ robustness to changing fab conditions, e.g., when lot size or train size changes. Flow line models are shown to be more accurate and robust than linear or affine models and require approximately 200 times less computation than detailed models.

Performance bounds for hybrid flow lines: Fundamental behavior, practical features and application to linear cluster tools

The anticipated transition to 450 mm diameter wafers provides the semiconductor manufacturing industry an opportunity to consider new equipment designs that address issues associated with small lot sizes and high mix production. One candidate design is the linear cluster tool. Compared to traditional circular cluster tools, linear cluster tools have advantages such as high flexibility and greater productivity. In this paper, we develop a simulation of cluster tools with realistic parameters, which incorporates rolling setups and wet cleans. We use the simulation to study the effect of rolling setups and wet cleans with different lot sizes and train levels. For the simulation based on data from a BlueShift cluster tool in production, the linear cluster tool has 5.22% and 4.09% greater throughput with rolling setups and both rolling setups and wet cleans, respectively.

Wafer admission control for clustered photolithography tools

For deterministic hybrid flow lines with multiple classes of customer and no overtaking, we develop upper bounds on the customer departure times. For this general class of systems, the bounds are the most that one can deduce; examples can be constructed where equality is achieved and where it is not. We incorporate a very general class of setups and similarly obtain upper bounds. Such hybrid flow lines are natural candidates to serve as models of cluster tools in semiconductor wafer manufacturing. We use the flow lines as a starting point for the development of approximation models for a relatively new class of cluster tools with linear flow, called linear cluster tools. The approximations include issues caused by wafer transport robots and rolling setups. The resulting approximations are of good quality; they predict the just-in-time (maximum) throughput to within about 5%. Computation requires two orders of magnitude less effort than detailed simulation. They may thus be useful for fabricator simulations.

Exit Recursion Models of Clustered Photolithography Tools for Fab Level Simulation

In semiconductor wafer manufacturing, clustered photolithography scanners frequently use pre-scan or post-scan wafer buffers to ensure that the scanner is seldom starved of wafers or blocked from further production. While such practice is essential to maximize the throughput of this costly tool, state-of-the-art methods for determining when to use the buffer are overly cautious. As a consequence, each wafers residency time in the tool may be significantly larger than necessary and the time a lot spends inside the cluster is increased. Since satisfaction of time windows and reduction in wafer residency time in a tool will arguably improve yield and reduced lot process time will increase manufacturing deployment opportunities, we strive to minimize residency time while maintaining maximum throughput. To achieve our goal, we develop wafer admission control algorithms considering setups and transient operation. The output of the algorithm is suggested wafer entry times to the tool and is intended to be used by the wafer handling robot as a guideline. We simulate several representative systems to verify the performance of the approach. For a typical system, it is shown that, while maintaining throughput, the wafer residency time, the lot process time and the wafer buffer occupancy are reduced by 54%, 31% and 67%, respectively. The lot deployment opportunity in the same case is increased by 14%. As a consequence, there are fewer wafers for the wafer handling robots to serve and the tool may be designed with fewer buffer slots. The concept and algorithm will thus improve clustered photolithography performance in numerous ways.

Performance Analysis of Multi-Product Bernoulli Lines with Dedicated Finite Buffers

In semiconductor wafer fabricators (fabs), clustered photolithography tools (CPTs) are often the bottleneck. With a focus on fab-level simulation, we propose a new class of equipment models for CPTs called exit recursion models (ERMs). These models are inspired by concepts from flow line theory. We describe the intuition behind ERMs and provide the parameterization and simulation equations. These ERMs are data-driven empirical models and we develop three types based on different data perspectives: 1) tool log; 2) wafer log; and 3) lot log. To assess the quality of the proposed models, we conduct three classes of simulation experiments. A detailed CPT model, an affine model, and an empirical flow line model are used as the baselines. We consider mean cycle time, lot residency time, throughput time, and computation time as our primary performance metrics. The results suggest that ERMs are more accurate and robust than the affine models for all metrics and sometimes rival the performance of the empirical flow line models considered. ERMs require about 1.9 times as much computation as an affine model and about 250 times less computation than an empirical flow line model. ERMs may be helpful to increase the accuracy of fab-level simulation results without significant additional computation.