L. Arnone

Euclidean distance soft-input soft-output decoding algorithm for low-density parity-check codes

A new antilog-sum algorithm for decoding error-correcting codes is described. The soft-input, soft-output (SISO) algorithm uses squared Euclidean distance as the metric, does not require knowledge of the signal-to-noise ratio of the received signal and is less complex to implement than other SISO algorithms. The results of simulations show that the performance is very close to that of the log-sum-product algorithm.

Fast Fourier Transform simplified soft-distance decoding algorithm for decoding non-binary LDPC codes

Non-Binary Low-Density Parity-Check (NB-LDPC) codes have been shown to outperform equivalent LDPC codes defined over the binary field, especially when they are designed in high order Galois fields GF(q). This however leads to an increased decoding complexity. In this paper, a computationally efficient version of a soft distance algorithm used for decoding (NB-LDPC) error-correcting codes is described. This decoding algorithm uses squared Euclidean distance as the metrics, does not require knowledge of the signal-to-noise ratio of the received signal, and is less complex to implement than the Fast Fourier Transform Sum-Product and the log-sum-product algorithms. It is a simplified algorithm that can be easily implemented on programmable logic technology such as Field Programmable Gate Array (FPGA) devices because of its use of only additions, subtractions and look-up tables, avoiding the use of quotients and products. Simulations results show that the performance is the same as or better than that of the Fast Fourier Transform Sum-Product and the log-sum-product algorithms. Simulations were done over the AWGN, Rayleigh Fading and impulsive noise with a Symmetric Alpha-Stable (SαS) distribution channels.

FPGA implementation of two very low complexity LDPC decoders

Low-Density Parity-Check (LDPC) codes are very efficient error control codes that are being considered as part of many next generation communication systems. In this paper FPGA implementations of two low complexity decoders are presented. These two implementations operate over any kind of parity check matrix, (including those randomly generated, structurally generated, either systematic or non systematic) and can be parametrically performed for any code rate k/n. The proposed implementations are both of very low complexity, because they operate using only sums, subtracts and look-up tables. One of these decoders offers the advantage of not requiring the knowledge of the signal-to-noise ratio of the channel, as it usually happens to most of decoders for LDPC codes.

Soft Distance Metric Decoding of Polar Codes

In this paper, we implement the Successive Cancellation SC decoding algorithm for Polar Codes by using Euclidean distance estimates as the metric of the algorithm. This implies conversion of the classic statistical recursive expressions of the SC decoder into a suitable form, adapting them to the proposed metric, and properly expressing the initialization values for this metric. This leads to a simplified version of the logarithmic SC decoder, which offers the advantage that the algorithm can be directly initialised with the values of the received channel samples. Simulations of the BER performance of the SC decoder, using both the classic statistical metrics, and the proposed Euclidean distance metric, show that there is no significant loss in BER performance for the proposed method in comparison with the classic implementation. Calculations are simplified at the initialization step of the algorithm, since neither is there a need to know the noise power variance of the channel, nor to perform complex and costly mathematical operations like exponentiations, quotients and products at that step. This complexity reduction is especially important for practical implementations of the SC decoding algorithm in programmable logic technology like Field Programmable Gate Arrays FPGAs.

An improved hardware implementation of the one hot Residue Number System

Residue Number System (RNS) is a kind of numerical representation that allows to divide a given arithmetic operation done over a binary numerical representation with a determined number of bits, into several smaller operations that are performed in parallel, and use binary numerical representations of smaller number of bits. There are many possible implementations of RNS, but the one of highest processing speed is the so called One Hot Residue Number System (OHRNS). The main disadvantage of this implementation is that it requires order m2 number of transistors for a modulo-m operation. In this paper a modified version of OHRNS, called OHRNS2 is presented, which perform as well as the original OHRNS, but with significant less hardware requirements. A generalized system is also presented, and called OHRNSn.