L. Date

HKMG process impact on N, P BTI: Role of thermal IL scaling, IL/HK integration and post HK nitridation

NBTI and PBTI are studied in IL/HK/MG gate stacks having EOT down to ~ 6Å and fabricated using low T RTP based thermal IL and a novel IL/HK integration. At equivalent EOT, proposed stacks provide improved NBTI and similar PBTI when compared to conventional Chem-Ox IL based HKMG stacks. EOT scaling achieved by RTP thermal IL scaling shows lower rate of increase in NBTI and PBTI when compared to Chem-Ox IL scavenged stacks. Impact of Nitrogen and role of post HK nitridation are studied. Physical mechanism of improved BTI in proposed stacks is discussed in detail.

Composition and Growth Kinetics of the Interfacial Layer for MOCVD HfO2 Layers on Si Substrates

To boost MOS transistor performance, thickness of the gate dielectric is continuously scaled down. This results in an increase of gate tunneling leakage current, which at some point prevents further downscaling. Desired parameters of alternative materials to SiO 2 are a higher dielectric constant (high-k materials), stability, and compatibility with silicon. A general observation for one of the prime candidates. HfO 2 , is formation of an interfacial layer between the silicon and the high-k material that limits scalability because of its low k-value. Hence, a thorough study of the formation of this layer and its contribution to the equivalent oxide thickness is of utmost importance. We studied the composition and growth kinetics of the interfacial layer formed during the deposition of HfO 2 by metallorganic chemical vapor deposition using O 2 and tetrakis-diethylamidohafnium as precursor. We found the composition and thickness of the interfacial layer to be dependent on the deposition parameters as well as on the starting surface. The layers composition is hafnium silicate-like and its thickness increases as a function of deposition time and temperature. It is therefore controlled by deposition of the HfO 2 layer.

Effect of SiN on Performance and Reliability of Charge Trap Flash (CTF) Under Fowler–Nordheim Tunneling Program/Erase Operation

Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P- and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.

Impact of SiN Composition Variation on SANOS Memory Performance and Reliability Under nand (FN/FN) Operation

Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N+) to Si-rich ( Si+) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant over erase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si+ SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si+ SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND flash applications.

Scaled Gate Stacks for Sub-20-nm CMOS Logic Applications Through Integration of Thermal IL and ALD HfOx

The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on negative-bias temperature instability and positive-bias temperature instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to ~6Å, with excellent gate leakage, mobility, and world-class BTI. The mechanism responsible for improved BTI is discussed.

Impact of Top-Surface Tunnel-Oxide Nitridation on Flash Memory Performance and Reliability

Two approaches to top-surface nitridation of tunnel oxide, i.e., rapid thermal nitridation using NH3 anneal and decoupled plasma nitridation, are compared. Floating-gate MOS capacitors with source/drain were used to evaluate Flash memory performance and reliability. Tunnel-oxide NH3 anneal degrades postcycling retention performance compared to plasma nitridation for the same equivalent oxide thickness reduction. The poorer performance of NH3 anneal is related to higher N incorporation into SiO2 bulk rather than top surface. Postcycling memory erase-level shift and memory window (MW) closure is lower for plasma nitridation compared to NH3 anneal. A new integration scheme using plasma nitridation followed by NO anneal produces the lowest MW closure with cycling.

High-k materials for advanced gate stack dielectrics: a comparison of ALCVD and MOCVD as deposition technologies

In the quest for ever smaller transistor dimensions, the well-known and reliable SiO 2 gate dielectric material needs to be replaced by alternatives whith higher dielectric constants in order to reduce the gate leakage. Candidate materials are metal oxides such as HfO 2 . Themost promising deposition techniques, next to Physical Vapor Deposition, appear to be ALCVD and MOCVD. In this paper, we compare the most important characteristics of layers from both proces techniques and assess their relevance to gate stack applications: density, crystallisation, impurities, growth mechanism, interfacial layers, dielectric constant, mobility. Although we find some minor differences, layers from both techniques mostly show striking similarities in many aspects, both positive and negative.

O 2 post deposition anneal of Al 2 O 3 blocking dielectric for higher performance and reliability of TANOS Flash memory

TANOS Charge Trap Flash approach (CTF) is a candidate to replace Floating Gate approach (FG) for sub-32 nm technology node. However the main challenge for TANOS is its poor retention characteristics. In this paper, we show that by performing an O2 anneal after Al2O3 deposition the charge retention is considerably improved as well as the other memory characteristics: program, erase, endurance.

Nitric oxide rapid thermal nitridation for Flash memory applications

Rapid thermal annealing in nitric oxide (RTNO) has long been used for the formation of ultrathin silicon oxynitride gate dielectrics. Nitric oxide (NO) furnace anneals are used in the formation of floating gate Flash memory transistor tunnel oxides. Nitrogen is thus, incorporated to improve the oxide reliability during program/erase cycling endurance and data retention. We present here a study of rapid thermal annealing and oxide growth in nitric oxide using Applied Materials single-wafer rapid thermal process (RTP) that enables the RTNO anneal to operate at higher temperatures compared to furnace, thereby allowing two times greater incorporation of nitrogen at the silicon/silicon dioxide interface. At 1200°C, a greater than 11% peak interface nitrogen concentration as measured by secondary ion mass spectroscopy (SIMS) in a 75 Angstrom SiON film is achieved. Reliability testing using a floating gate flash memory capacitor with minority carrier source (implants) test vehicle shows that this increase in the peak interface nitrogen results in an improvement in the tunnel oxides program/erase cycling endurance and data retention. For future memory devices, for example 3D memory devices, the use of direct RTNO oxide growth for dielectric formations is possible. In this case, higher temperatures allow the growth of thicker oxides in pure NO at 1200°C, with greater nitrogen incorporation.

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Program/Erase (P/E) cycling endurance in poly-Si/Al2O3/SiN/SiO2/Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (VFB) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.