L. Manchanda

Rapid thermal oxidation of silicon in N2O between 800 and 1200 °C: Incorporated nitrogen and interfacial roughness

Oxynitrides can suppress the diffusion of boron from the polycrystalline silicon gate electrode to the channel region of an ultralarge scale integrated device, and are therefore important potential substrates for thin SiO2 gates. Direct oxynitridation of Si in N2O is a simple and manufacturable N incorporation scheme. We have used rapid thermal oxidation to grow O2‐ and N2O‐oxides of technological importance (∼10 nm thick) in the temperature range 800–1200 °C. Accurate measurements of the N content of the N2O‐oxides were made using nuclear reaction analysis. N content increases linearly with oxidation temperature, but is in general small. A 1000 °C N2O‐oxide contains about 7×1014 N/cm2, or the equivalent of about one monolayer of N on Si (100). Nonetheless, this small amount of N can retard boron penetration through the dielectric by two orders of magnitude as compared to O2‐oxides. The N is contained in a Si‐O‐N phase within about 1.5 nm of the Si/SiO2 interface, and can be pushed away from the interface...

Etching of high-k dielectric Zr1−xAlxOy films in chlorine-containing plasmas

As new, advanced high-k dielectrics are being developed to replace SiO2 in future generations of microelectronics devices, understanding their etch characteristics becomes vital for integration into the manufacturing process. We report on the etch rates and possible mechanisms for one such dielectric, Zr1−xAlxOy (x≈0.2), in plasmas containing a mixture of Cl2 and BCl3, as a function of gas composition and ion impact energy. Higher concentrations of BCl3 enhance the etch rate as well as selectivity of Zr1−xAlxOy etching as compared to the etching of α-Si, whereas increasing ion energy increases the etching rates but decreases selectivity. In a high density helical resonator plasma, etching rates on the order of 700 A/min and 1:1 selectivity are typical. Angle-resolved x-ray photoelectron spectroscopy was used to study the composition of the upper ∼30 A of the film, before and at the end of the etching process. We found that the etching rate of Zr1−xAlxOy does not change with time for the range of Cl2/BCl3 ...

Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

To sustain the silicon CMOS scaling beyond 100 nm, an alternate gate dielectric with K>7 is needed. The deposited high K dielectrics (metal oxides) have nonstoichiometric composition and therefore have large electrical defects (traps) in the bulk of the dielectric and at the dielectric/semiconductor interface. In this paper, we report a novel doping method to quench traps in thin films of Al/sub 2/O/sub 3/ (K>8). By adding small amounts of dopants such as Zirconium (Zr) or Silicon (Si), we have achieved /spl sim/10nm thick aluminum oxide films with record low leakage current (<10/sup -13/A/mm/sup 2/) and ultra-thin (3-5 nm) aluminum oxide films with 2 very low interface state density (/spl sim/10/sup 10//cm/sup 2/-eV) at the silicon/aluminum oxide interface. We propose a physics based model for the doping effect and selection of dopants for metal oxides with K>10.

Si-doped aluminates for high temperature metal-gate CMOS: Zr-Al-Si-O, a novel gate dielectric for low power applications

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates. These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology. In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20. With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/1.2 nm with leakage current <50 mA/cm/sup 2/ and gate power budget <50 mW/cm/sup 2/, at IV. For high performance, low power CMOS, beyond SiO/sub 2/, doped-aluminum oxide (with K/spl sim/10) may be a viable alternate gate dielectric. Beyond aluminum oxide, aluminates (with K>15) may be viable alternate gate dielectrics.

Growth temperature dependence of the Si(001)/SiO2 interface width

The growth temperature dependence of the thin thermally oxidized Si(001)/SiO2 interface width was studied using synchrotron x‐ray diffraction. Nine samples with oxide thickness of about 100 A were studied, with growth temperatures ranging from 800 to 1200 °C. The oxides were prepared by rapid thermal oxidation. We found that interfacial roughness decreases linearly with increasing growth temperature, with a measured interface width of 2.84 A for the sample grown at 800 °C, and 1.76 A when grown at 1200 °C.

Crystallization kinetics in amorphous (Zr0.62Al0.38)O1.8 thin films

Thin films of Zr0.62Al0.38O1.8 are amorphous when deposited at room temperature by rf magnetron sputtering. Crystallization occurs during subsequent annealing in the temperature range of 700–1000 °C for times in the range of 10 s–100 h. The crystallite size and the fraction of the sample that had crystallized were determined using x-ray diffraction. The films were found to initially develop a low density of fairly large (∼8 nm) crystallites, while subsequent heat treatment was found to increase the density rather than the size of the crystallites. Crystallization can be described with a first-order rate equation; the rate constant is exponential in temperature with an effective activation energy of 6.6 eV. Films given a 10 s anneal at <850 °C develop a substantial density of 8 nm grains, making this specific composition an unsuitable candidate for replacing SiO2 as the gate oxide in hyperscaled field-effect transistors.

Impact of boron diffusion through O/sub 2/ and N/sub 2/O gate dielectrics on the process margin of dual-poly low power CMOS

This work evaluates the impact of boron penetration from p/sup +/-polysilicon on process margin and system performance. We experimentally demonstrate that small (3/spl sigma/=/spl plusmn/3 /spl Aring/) variations in gate oxide thickness, coupled with boron penetration, can increase the spread in threshold voltages by /spl plusmn/100 mV or more. By inhibiting boron penetration, N/sub 2/O grown oxides are shown to improve V/sub T/ control, thereby enhancing the process margin. We present a physically-based model to describe boron penetration as a function of t/sub ox/, and analyze the impact of increased V/sub T/ variation on subthreshold leakage current and on the resultant off-state power consumption.<<ETX>>

A new method to fabricate thin oxynitride/oxide gate dielectric for deep submicron devices

Abstract In this paper, we report a new method to fabricate oxynitride/oxide gate dielectrics for MOS devices. This method utilizes a thin layer of oxynitride as a membrane for controlled diffusion of O 2 and oxidation of Si at high temperatures with low thermal budget. MOS devices made with these oxynitride/oxide structures have interface properties like thermal SiO 2 with a structure resistant to boron diffusion.

A boron-retarding and high interface quality thin gate dielectric for deep-submicron devices

We report the fabrication and device characteristics of a 50 /spl Aring/ thick dual-layer gate dielectric with high interface quality (D/sub it/ and Q/sub f/ /spl sim/10/sup 10/ cm/sup 2/) and capable of retarding boron penetration. This dual-layer dielectric is formed by low temperature CVD deposition of a /spl sim/40 /spl Aring/ thick oxynitride layer, through which slow O/sub 2/ diffusion is used to grow a /spl sim/10 /spl Aring/ thick SiO/sub 2/ at the interface. The small thickness of the SiO/sub 2/ layer reduces the oxidation time at high temperature, thus reducing the required thermal budget. The top oxynitride retards boron penetration and the thin SiO/sub 2/ layer provides a high quality interface. The channel mobility of NMOS devices with this dual dielectric is equal to the mobility of devices with a RTO dielectric grown at 950/spl deg/C.<<ETX>>