L. Miguel Silveira

Efficient computation of the worst-delay corner

Timing analysis and verification is a critical stage in digital integrated circuit design. As feature sizes decrease to nanometer scale, the impact of process parameter variations in circuit performance becomes extremely relevant. Even though several statistical timing analysis techniques have recently been proposed, as a form of incorporating variability effects in traditional static timing analysis, corner analysis still is the current timing signoff methodology for any industrial design. Since it is impossible to analyze a design for all the process corners, due to the exponential size of the corner space, the design is usually analyzed for a set of carefully chosen corners, that are expected to cover all the worst-case scenarios. However, there is no established systematic methodology for picking the right worst-case corners, and this task usually relies on the experience of design and process engineers, many times leading to over design. This paper proposes an efficient automated methodology for computing the worst-delay process corners of a digital integrated circuit, given a linear parametric characterization of the gate and interconnect delays.

ARMS - automatic residue-minimization based sampling for multi-point modeling techniques

This paper describes an automatic methodology for optimizing sample point selection for using in the framework of model order reduction (MOR). The procedure, based on the maximization of the dimension of the subspace spanned by the samples, iteratively selects new samples in an efficient and automatic fashion, without computing the new vectors and with no prior assumptions on the system behavior. The scheme is general, and valid for single and multiple dimensions, with applicability on rational nominal MOR approaches, and on multi-dimensional sampling based parametric MOR methodologies. The paper also presents an integrated algorithm for multi-point MOR, with automatic sample and order selection based on the transfer function error estimation. Results on a variety of industrial examples demonstrate the accuracy and robustness of the technique.

Generating realistic stimuli for accurate power grid analysis

Power distribution systems in integrated circuits are used to provide the voltages and currents the devices need to operate properly. As the semiconductor industry moves into deep nanometer nodes, problems like voltage drop, ground bounce and electromigration which may cause chip failures, are worsening, as more devices, operating at higher frequencies are placed closer together. Verification of a power distribution system is therefore paramount to silicon success. This type of verification is usually done by simulation, targeting a worst-case scenario, typically characterized by the almost simultaneous switching of several devices in the circuit. The definition of the worst-case situation is therefore crucial, since it influences the result of the simulation and ultimately the design target. Supposedly safe but unrealistic settings such as assuming that all signals switch simultaneously, could lead to costly over-designs in terms of die area. In this paper we describe a software tool that generates a reasonable, realistic, worst-case set of stimuli for simulation, based on timing and spatial restrictions that arise from the circuits netlist and placement. Generating such stimuli is akin to performing a standard static timing analysis, as is done before signoff so the tool fits well within conventional design frameworks. The resulting stimuli indicates that only a fraction of the gates change in any given timing window, leading to a more robust verification methodology, specially in the dynamic case.

Generating Worst-Case Stimuli for Accurate Power Grid Analysis

Power distribution systems provide the voltages and currents that devices in a circuit need to operate properly and silicon success requires its careful design and verification. However, problems like voltage drop, ground bounce and electromigration, which may cause chip failures, are worsening, as more devices, operating at higher frequencies, are placed closer together. Verification of this type of systems is usually done by simulation, a costly endeavor given the size of current grids, making the determination of the worst-case input setting a crucial task. Current methodologies are based on supposedly safe settings targeting either unrealistic simultaneous switching on all signals or heuristic accounts of the joint switching probability of nearby signals. In this paper we propose a methodology for computation of the worst-case stimuli for power grid analysis. This is accomplished by determining the input vector that maximizes the number of gates, in close proximity to each other, that can switch in a given time window. The addition of these temporal and spatial restrictions makes the solution of the underlying optimization problem feasible. Comparisons with existing alternatives show that only a fraction of the gates change in any given timing window, leading to a more robust and efficient verification methodology.

Extended Hamiltonian pencil for passivity assessment and enforcement for S-parameter systems

An efficient algorithmbased on the Extended Hamiltonian Pencil was proposed in [1] for systems with hybrid representation. Here we further extend the Extended Hamiltonian Pencil method to systems described with scattering representation, i.e. S-parameter systems. The derivation of the Extended Hamiltonian Pencil for S-parameter systems is presented. Some properties that allow passivity enforcement based on eigenvalue displacement are reported. Experimental results demonstrate the effectiveness of the proposed method.

Variation-Aware, Library Compatible Delay Modeling Strategy

Variability in digital integrated circuits makes timing verification an increasingly challenging task. Statistical static timing analysis has been proposed as a solution to this problem, but most of the work has concentrated in the development of timing engines for computing delay propagation. Such tools rely on the availability of delay formulas accounting for both cell and interconnect delay. In this paper, we concentrate on the impact of interconnect on delay and propose an extension to the standard modeling strategies that is variation-aware and compatible with such statistical engines. Our approach, based on a specific type of perturbation analysis, allows for the analytical computation of the quantities needed for statistical delay propagation. We also show how perturbation analysis can be performed when only the standard delay table lookup models are available for the standard cells. Results from applying our proposed modeling strategy to computing delays and slews in several instances accurately match similar results obtained using electrical level simulation

Issues in Model Reduction of Power Grids

Power grid analysis has recently risen to prominence due to the widespread use of lower supply voltages by power-conscious designs. Low supply voltages imply smaller noise margins and make the voltage drop across the power grid very critical since it can lead to overall slower circuits, signal integrity issues and ultimately to circuit malfunction. Verifying proper behavior of a power grid is a difficult task due to the sheer size of such networks. The usual solution to this problem is to apply reduced-order modeling techniques to generate a smaller macromodel. These techniques are typically based on projections to subspaces whose dimension is determined by the input space. Unfortunately power grids are characterized by a massive number of network ports, which limits the amount of compression achievable. Recently, new algorithms have been proposed for solving this problem which may provide efficient alternatives. In this paper we discuss the main issues related to model reduction of power grid networks and compare several methods for such reduction, providing some insight into the problem and how it can be tackled.

Parametric structure-preserving model order reduction

Analysis and verification environments for next- generation nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects, such as process variations and Electromagnetic (EM) couplings. Designed-in passives, substrate, interconnect and devices can no longer be treated in isolation as the interactions between them are becoming more relevant in the behavior of the complete system. At the same time variations in process parameters lead to small changes in the device characteristics that may directly affect system performance. These two effects, however, can not be treated separately as the process variations that modify the physical parameters of the devices also affect those same EM couplings. Accurately capturing the effects of process variations as well as the relevant EM coupling effects requires detailed models that become very expensive to simulate. Reduction techniques able to handle parametric descriptions of linear systems are necessary in order to obtain better simulation performance. In this work Model Order Reduction techniques able to handle parametric system descriptions are presented. Such techniques are based on Structure-Preserving formulations that are able to exploit the hierarchical system representation of designed- in blocks, substrate and interconnect, in order to obtain more efficient simulation models.

Positive realization of reduced RLCM nets

Model Order Reduction is nowadays routinely applied as a basic step in order to enable the efficient simulation of very large RLC linear models, such as extracted parasitics and circuit oriented EM extraction. Often, such reduced models are synthetized as a subcircuit and ported to simulation environments for multiple subsequent runs. Such an approach is quite common as often designers prefer to work with circuit netlists as opposed to abstract mathematical representations and furthermore, many simulators can only handle circuit elements. However, the potential advantages provided by the reduction may be compromised when the dense reduced models are synthetized to netlists due to the presence of non-physical elements (such as negative RLC) or a large number of controlled sources. Such issues may hinder efficiency or even completely preclude analysis as many simulators cannot handle non-physical elements whose handling is altogether questionable. This paper proposes a methodology for the synthesis of reduced order models of general multiport RLC nets amenable to be included in standard simulation environments. Unlike other previously published approaches, the methodology generates very compact models while guaranteeing the positiveness of the RLC values, which allows their direct confinement in any SPICE-like circuit simulator.

Efficient analysis of variability impact on interconnect lines and resistor networks

Continued technology scaling coupled with limited lithographic capabilities is a leading cause of increased design variability. In the nanometer regime lithography tools have failed to keep pace with Moores Law and printed feature sizes are a small fraction of the wavelength of light used in current processes. Such sub-wavelength printing makes features highly susceptible to perturbations in the lithographic process conditions which leads to printed designs exhibiting increased variability. Such variability directly affects design behavior and performance in multiple ways. One of the areas of concern is power grid (PG) design, where lithographic errors may locally modify the wire widths. These variations, that may affect any and all wires in the grid, have a critical impact on the power distribution across the chip, introducing considerable current fluctuations which are a potential cause for electromigration effects. To analyze and account for the impact of these errors requires a complete extraction of the PG, which generates a large resistive network, potentially with several million elements, whose simulation is computationally challenging. This paper proposes a fast and accurate variability analysis of very large resistor networks, such as PG extracted netlists, that allows estimating the effects of multiple parameter settings in reasonable time. The proposed model can be easily combined with Litho/CMP simulators in order to boost much needed design-aware lithography.