L.T. Smit

An energy-efficient reconfigurable circuit-switched network-on-chip

Network-on-chip (NoC) is an energy-efficient on-chip communication architecture for multi-tile system-on-chip (SoC) architectures. The SoC architecture, including its run-time software, can replace inflexible ASICs for future ambient systems. These ambient systems have to be flexible as well as energy-efficient. To find an energy-efficient solution for the communication network we analyze three wireless applications. Based on their communication requirements we observe that revisiting of the circuit switching techniques is beneficial. In this paper we propose a new energy-efficient reconfigurable circuit-switched network-on-chip. By physically separating the concurrent data streams we reduce the overall energy consumption. The circuit-switched router has been synthesized and analyzed for its power consumption in 0.13 /spl mu/m technology. A 5-port circuit-switched router has an area of 0.05 mm/sup 2/ and runs at 1075 MHz. The proposed architecture consumes 3.5 times less energy compared to its packet-switched equivalent.

Dynamic Reconfiguration in Mobile Systems

Dynamically reconfigurable systems have the potential of realising efficient systems as well as providing adaptability to changing system requirements. Such systems are suitable for future mobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate in dynamic application and communication environments. We propose an approach in which reconfiguration is applied dynamically at various levels of a mobile system, whereas traditionally, reconfigurable systems mainly focus at the gate level only. The research performed in the CHAMELEON project 1 aims at designing such a heterogeneous reconfigurable mobile system. The two main motivations for the system are 1) to have an energy-efficient system, while 2) achieving an adequate Quality of Service for applications.

Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

This work evaluates an algorithm that maps a number of communicating processes to a heterogeneous tiled system on chip (SoC) architecture at run-time. The mapping algorithm minimizes the total amount of energy consumption, while still providing an adequate quality of service (QoS). A realistic example is mapped using this algorithm.

Run-time Mapping of Applications to a Heterogeneous SoC

This paper presents an iterative hierarchical approach to map an application to a parallel heterogeneous SoC architecture at run-time. The application is modeled as a set of communicating processes. The optimization objective is to minimize the energy consumption of the SoC, while still providing the required quality of service. This approach is flexible, scalable and the performance looks promising.

Energy management for dynamically reconfigurable heterogeneous mobile systems

Dynamically reconfigurable systems offer the potential for realising efficient systems as well asproviding adaptability to changing system requirements. Such systems are suitable for futuremobile multimedia systems that have limited battery resources, must handle diverse data types, and must operate in dynamic application and communication environments. We propose an approach in which reconfiguration is applied dynamically at various levels of a mobile system, whereas traditionally, reconfigurable systems mainly focus at the gate level only. The research performed in the CHAMELEON project 1aims at designing such a heterogeneous reconfigurable mobile system. The two main motivations for the system are 1) to have an energy-efficient system, while 2) achieving an adequate Quality of Service for applications.

Implementation of a 2-D 8×8 IDCT on the Reconfigurable Montium Core

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a word-level reconfigurable Montiumreg processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM.

Soft output bit error rate estimation for WCDMA

This paper introduces a method that computes an estimation of the bit error rate (BER) based on the RAKE receiver soft output only. For this method no knowledge is needed about the channel characteristics nor the precise external conditions. Simulations show that the mean error of the estimation is below 2%, with only a small variance. Implementation issues for a practical use of the method are discussed.

BER Estimation for HiperLAN/2

This paper presents a method to estimate the bit error rate (BER) of the wireless channel based on statistical analysis of the soft output of the receiver only. In HiperLAN/2 several modulation schemes can be used. The system should select the most suitable modulation scheme dependent on the quality of the wireless link and the Quality of Service requirements of the user. Our BER estimation method can be used to estimate the current quality of the wireless link and the quality when another modulation mode is considered. With this information, it is possible to select the most suitable modulation scheme for the current situation.