L. Van Eycken

Fast adaptive filtering with special hardware

In this paper, a few aspects concerning the hardware implementation of adaptive filtering algorithms are discussed. Two different approaches to adaptive filtering are considered, each having their own hardware implications. The ideas that are developed are illustrated with some practical examples.

A Simple Arithmetic Processor For Image Operations

This paper describes a hardware module to be a part of a general image computer that is being developed in our laboratory. The design of this module was started to provide us with a powerful processor suited for several classes of image filtering operations on a single board at a very high speed and also to gain insight and experience in hardware that is suitable for adaptive filtering of images. A prototype of the module is now being built.

Real-Time Image Computer Configuration

In order to adapt to the steady growth of modern communication requirements in information processing, the overall computing power is being decentralised to special purpose intelligent terminals. In contrast to the well developed graphic displays, the currently available image displays have very little processing capabilities. The complexity and volume of imagery requires a special approach to enable real-time processing. In this paper a new image computer, called UPIC is proposed which features rather general image processing capabilities at television rates combined with powerful interactive computer graphics.

The Time-Shared Bus: A Viable Way To Image Multiprocessing

Out of all possible multiprocessor interconnection schemes, the time-sleazed bus ias some advantages for hardware realisations. Not only is it one of the simpliest and cheapest ways to tie processors together, but it is also an ideal interconnection scheme if one wants to keep the structure flexible and modular. On the other hand, the main disadvantage of the time-shared bus is the limited bandwidth. Especially in image processing, this can be very troublesome. This paper will try to explore the possibilities of a time-shared bus in this field of application. A process is divided into a set of processors, each with a specified number of inputs and outputs. Furthermore, each processor is determined by a set of delays between these inputs and outputs. The model is characterised by four parameters: - the delays per processor - the constancy of the delays - the use or no use of internal memory in a processor - the fact whether the operations on a processor are pipelined or not. These parameters influence the complexity and the effectiveness of the hardware. Using them to classify different hardware approaches, we develop a hardware definition of a time-shared bus, that optimises the use of that bus in order to diminish the disadvantage of the limited bandwidth. An example of a process, constructed by putting processors in pipeline and/or in parallel, illustrate the possibilities.

Two Approaches To Transform Coding Using Classified Vector Quantization

In this paper, two approaches of classified transform coding using vector quantization are presented and discussed. The image data, which are known to be statistically uncertain, are classified before any further quantization and coding operations. The local image activities can be ascertained either by using the neighboring decoded data e. finite-state method) or by examining the current data (i. e. activity-detection method). The finite-state method, which is more preferable to he implemented using small transform blocks (typically 4 x 4) due to the fact that the inter-block correlations decrease for larger block dimensions, provides satisfied data classifications without requiring extra indication bits. The activity-detection method is however more likely to have larger transform blocks in order to keep the number of the extra indication bits at a reasonable level. Other practical considerations for both methods are also given.

A New Coding Method For Low Bit-Rate Video Signals

In this paper, a hybrid motion evaluation coder for low bit-rate (64 Kb/s) video sequence transmission is studied. More than one previous frames are used to estimate the temporary motion behavior in the motion evaluation process (rather than conventional motion estimation methods in which only the immediate former frame is used). The motion sequence is therefore estabished alongside the image data sequence. Through investigating and analysing the previous frame of this motion sequence, which are available to both the coder and the decoder, the moving objects can be identified from the background. The current image frame to be encoded is then divided into two types of regions: the background region which may not he transmitted at all but simply repeated with the data of the previously decoded frame, and the moving region which is encoded by compensating the motion information. The moving region is reconstructed in the normal frame sampling frequency while the background data are treated coarsely by refreshing them in a much lower frequency. The relative impact of the moving region with regard to the background region is also evaluated for assigning bits to the two separated regions. As long as this impact is significant enough, the background data may remain unchanged. The final reconstructed image frame is then the coarsely processed background superimposed by the decoded moving objects.

Adaptive Coding For Image Sequences In Transform Domain Based On A Classification Strategy

This paper presents an adaptive coding technique, based on a classification strategy, for color image sequence signal. Due to the classification process, carried out in the data domain, the non-stationary image data are partitioned into different classes characterized by the local spatial activities. The coding process is then optimized in each class. The low-passed image data are coded from two processing loops: a dynamic one in which an image block is obtained by using motion-estimation; a static loop in which a best matched vector from a vector quantization sub-codebook is chosen. The motion estimated data block, on the other hand, contains also the classification information. The difference data are then adaptively encoded by using the classification informations, and the properties of the human visual system can be incorporated in order to increase the performance.

A Fast Full Parallel Interface Between A VAX Computer And A VERSAbus Based Real Time Image Computer

A fast full parallel interface adapted to VERSAbus has been designed and specifically optimized for image data transfers between a VAX computer with a DR11-W and a special purpose image computer. The interface has been built around a AM9516 chip, and contains all features to optimize the bus occupation, the data transfer speed as well as the microprocessor over-head. Special features of the interface are (1) easy handling of two-dimensional image ar-rays, (2) all communication via one parallel link including all commands (no additional serial link), and (3) high speed data transfer possibility of up to 600 Kbyte/sec. A software shell is being designed on the VAX computer to provide a userfriendly and efficient environment for the software and the application groups of our department. So, all communication between the VAX computer and the image computer will be made easier.

Adaptive Linear Filtering and Morphological Image Operations with the Filter Processor

Abstract A new image computer was developed in our laboratory. It has a modular structure, allowing us to tune the machine to the application for which it will be used. One of the modules, the filter processor, will be presented in this paper. It was designed to enlarge the power of our image computer and to gain insight and experience in hardware that is suitable for adaptive filtering of images. The module operates on images stored in memory modules, providing capabilities such as normal linear filtering, adaptive linear filtering, binary and greylevel morpholog ical filtering (erosion and dilation). The design resulted in a single board, high speed processor.

A Microprogrammable Processor Architecture For Image Processing

Because it is nearly impossible with todays technology to make a processor which is optimised for all possible image processing tasks one tries to realize different processors each of them being a compromise between technology, processing speed and class of operations that must be performed optimaly. This paper describes a hardware module to be part of a general image computer that is being developed in our laboratory. The design of this single board module was started to provide us with a flexible and high speed processor reprogrammable for several classes of image operations. To some extend this processor will be useful in hierarchical structures which seem to be very promising concepts at our days.