Lai Jiang

Adaptive Lifting Scheme for ECG QRS complexes detection and its FPGA implementation

For ECG QRS complexes detection, an Adaptive Lifting Scheme (ALS) has been developed and successfully implemented in Field Programmable Gate Array (FPGA). Realized under XUP Virtex-II Pro environment, the system consists of Top Configuration Module, Detection module and ALS module. Tested by the samples generated from the MIT-BIH ECG Database, its detection accuracy is higher than 99.681%, fulfilling ECG signal processing requirements. Comparing with the same algorithm realized with C codes under TIs TMS320VC5509A DSP system, more than 20% of processing time is saved.

System optimization of a 5.8 GHz ETC receiver using Memetic algorithm

ETC (Electronic Tolling Collection) systems develop rapidly in China in order to relieve the traffic congestion. As the key component of the ETC system, the design of the Radio Frequency (RF) transceiver is usually a tedious and experienced based work due to its high non-linearity. An automatic system level optimization method based on Memetic algorithm (MA) is proposed in this paper. A fitness function describing the relationship between receiver output signal-to-noise ratio (SNRout) and 9 system level parameters was derived and was optimized by the MA method. The correctness of the MA method was verified by the ADS simulation. A close result was obtained and the effects of the 9 parameters on the SNRout were discussed. The future design of the whole transceiver system can be based on this method.

A 31µW ask clock and data recovery circuit for wireless implantable systems

Amplitude shift keying (ASK) and pulse position modulation (PPM) can be used to provide self-synchronized data and clock for wireless implantable neural recoding systems, and therefore simplifies the complexity of the implanted circuits. In this paper, a novel extremely low power receiver designed for such a scheme is discussed. The integrated receiver utilizes inductive load implemented by PMOS device to boost the voltage gain of the front end amplifier. A charge-pump based CDR circuit is utilized to extract the clock and non-return-to-zero (NRZ) data directly from the demodulated waveform, and the required reference voltage is adaptively generated to cover a large data rate range. The receiver design is validated using 0.25 µ m CMOS technology. It exhibits a sensitivity of ∼1mV at 1.5MHz, covers an input data rate between 7kbit/s and 45.5kbit/s, and consumes only ∼31µW of power.

A CMOS time-to-digital converter for multi-voltage threshold method in positron emission tomography

Avoiding use of traditional high-speed analog-to digital converters (ADCs) and constant fraction discriminators, multi-voltage threshold (MVT) method is able to digitally sample positron emission tomography (PET) scintillation pulse with reasonable cost. As the key component of the MVT method, a time-to-digital convertor (TDC) with high resolution and large dynamic range is presented in this work. The TDC architecture uses a delay locked loop (DLL) to generate the fast clock edges from a 100 MHz clock, and a 32-stage Vernier delay lines (VDL) is used to achieve the 40pS timing resolution. The proposed TDC is designed using the standard 0.25 μm CMOS technology with 2.5V normal supply voltage. The power consumption of the TDC is ~70 mW.

Design of low power CMOS band-pass Gm-C filter for 5.8 GHz RF transceiver of ETC system

Since electronic tolling collection (ETC) allows vehicles passing through without slowing down which improves greatly transportation efficiency, it is chosen as the basic technology for new national highway network construction. The key component of the ETC system is a 5.8 GHz RF transceiver that enables wireless communication between toll booth and vehicles. A 1-V Gm-C sixth order band pass filter is designed in a 0.18 mm CMOS process for this purpose. Based on a pseudo differential operational transconductance amplifier (OTA), a wide tuning range and large input voltage swing is achieved. A common-mode feed forward (CMFF) circuit is introduced to reduce the distortion caused by common mode signal. The filter is implemented as a cascade of three identical second-order blocks. The power consumption is about 456 µW.

Design of a low power high speed auto-zeroed column-level ADC for data readout of CMOS APS based vertex detector

CMOS active pixel sensors have been proved to be promising technique for next generation vertex detector. As a good spatial resolution is required by the vertex detector, a column-based fully offset compensated 5-bit Analog-to-Digital Converter has been designed. The ADC is based on successive approximation architecture. In order to avoid use a large binary capacitor array, multiple references are used. Charge redistribution is achieved by applying different reference voltages. All the three dynamic reference voltages are independent and adjustable externally, which gives access to compensate the undesirable errors bit by bit. An external adjustable threshold value is used for triggering the conversion. An auto-zeroed sample and hold block has been designed to work in parallel with the ADC so that pipeline delay is avoided. The size of the whole system is 25 µm × 1 mm. Simulation results show that the sampling rate reaches 4 MSa/s and the power dissipation of analog components is less than 300 µW while working.

A FPGA-Based Real Time QRS Complex Detection System Using Adaptive Lifting Scheme

This paper presents a real time QRS wave detection system implemented using the FPGA. Based on the Adaptive Lifting Scheme, the digitized ECG sequence is directly processed in the spatial domain, thus greatly simplifies the system design and reduces the memory usage. In order to synchronize the input ECG sampling data and the FPGA based ALS system, a pipeline architecture interface is proposed. It works as a buffer and the ECG data is processed in a real time manner. The system is implemented on the XUPV5-LX110T evaluation platform, and validated by using ECG samples from the MIT-BTH Arrhythmia Database. Experimental results show that the system achieves 98.688% detection accuracy, while the dynamic power consumption is only ~20mW.

A Low-IF 2.4 GHz Integrated RF Receiver for Bluetooth Applications

In this paper, a low-IF 2.4 GHz integrated RF receiver for Bluetooth is presented. Designed in a 0.18 μm CMOS technology, the receiver consists of LNA, mixer, complex band-pass filter, and GFSK demodulator. A received signal strength indicator is also employed in the receiver to auto adjust the receiver gain. In this paper, the structures of the major modules were analyzed, and the simulation results are presented and discussed.

Design of Low-Power Standard Cell Library for High Efficient Energy Saving System

This paper presents an analytical method of low power standard cell library design for high efficient energy saving system. Based on the optimization of P/N width ratio, this method reduces both transistor size and power consumption in order to improve the energy efficiency of basic building blocks in the library. The library was realized in a 180 nm standard CMOS process and the maximum operating frequency is 50 MHz. In order to verify its performance, the library was applied to build an 8-bit adder using digital ASIC component development flow. The results show that a reduction of 43% power consumption was achieved. The library and the corresponding design flow developed in this paper meet the requirements of high efficient energy saving system design.

A 3rd order Opamp-Based Tunable Low-Pass Filter Design for Data Demodulator of a 5.8 GHz ETC RF Receiver

Electronic tolling collection (ETC) will be applied in the construction of the new national highway network in China and the Chinese standard has been released. A 5.8 GHz receiver satisfied the standard is one of the key components in the ETC system. In this work, a 3rd order low-pass filter was designed in a 0.18 μm CMOS process for the data demodulation block of the receiver. An operational amplifier was firstly realized and then a tunable low pass filter was designed based on the amplifier. Detailed simulation results are presented and the main design issues were discussed.