Lait Abu Saleh

Integrated circuit with memristor emulator array and neuron circuits for neuromorphic pattern recognition

This paper details an array of switch resistor based memristor emulators with integrate & fire based neuron ASIC for the development of memristor based pattern recognition. The designed ASIC has 4 memristor emulators with a conductance range from 195 nS to 190 uS; processing has been planned to be off-chip to get the freedom of programmability of any function in ASIC. The ASIC has 2 integrate and fire (I & F) neuron circuits which are planned to be used in conjunction with memristors in a large multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neurons and an algorithm of pattern recognition simulated in Ltspice. The ASIC has been fabricated in AMS 350nm process.

Integrated Circuit with Memristor Emulator Array and Neuron Circuits for Biologically Inspired Neuromorphic Pattern Recognition

This paper details an application-specific integrated circuit (ASIC) with an array of switched-resistor-based memristors (resistor with memory) and integrate & fire (I & F) neuron circuits for the development of memristor-based pattern recognition. Since real memristors are not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has five memristor emulators with one having a conductance range from 4.88ns to 4.99μs (200kΩ to 204.8MΩ) and other four having conductance ranging from 195ns to 190μs (5.2kΩ to 5.12MΩ). Signal processing has been planned to be off-chip to get the freedom of programmability of a wide range of memristive behavior. This paper introduces the memristor emulator and the realization of synapse functionalities used in neuromorphic circuits such as long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has two I & F neuron circuits which are intended to be used in conjunction with memristors in a multiple chip network for pattern recognition. This paper explains the memristor emulator, I & F neuron circuit and a respective neuromorphic system for pattern recognition simulated in LTspice. The ASIC has been fabricated in AMS 350nm process.

Programmable memristor emulator ASIC for biologically inspired memristive learning

This paper details a fully programmable floating memristor (resistor with memory) emulator ASIC designed for biologically inspired memristive learning. Since real memristor is not commercially available, a compact memristor emulator is needed for device study. The designed ASIC has a memristor emulator with conductance range from 4.88nS to 4.99μS (200KΩ to 204.8MΩ). The memristor emulator is a switched-resistor based circuit with processing performed off-chip in a FPGA. The processing has been planned to be off-chip to get the freedom of programmability of any function. This paper explains the memristor emulator and the realization of synapse functionality used in neuromorphic circuits like long term potentiation (LTP), Long Term depression (LTD) and synaptic plasticity. The ASIC has been designed and fabricated in AMS 350nm process.

Wireless Energy and Data Transmission ASIC for Blood Pressure Measurement in an Aneurysm Implant

Aneurysm implant requires multiple pressure sensors integrated into the stent graft for recording pressure profile inside an aneurysm sac. This paper details the design of an ASIC which receives power wirelessly using inductive coupling, fetches pressure data from a seperate chip and transmits data wirelessly. Besides, the ASIC extends the functionality of the external pressure measurement chip to support up to four pressure sensors by using an analog multiplexer. Error detection and forward error correction are implemented to improve data integrity for wireless data transmission. The design has been implemented and tested in 350 nm CMOS technology.

Comparison of single ended and differential signalling for wired biomedical implants using SPI communication with Reed Solomon Error Correction codes

For an implantable system for the recording of brain signals from neonatal mice the design specifications for the weight and the size of a implantable system are very tough. The animals are very small and light weight (1–3 cm, 2– 3 g) and the recording data rate is very high (3,5 Mbit/s). Thus, the system has to be extremely small. With state of the art technique it is not possible to set up a wireless implantable system that is suitable for a neonatal mouse. Thus a wired system is developed. For the wired system the connector is a size limiting factor. In wired transmission systems single ended and differential signalling are available. Differential signalling is more robust against noise disturbances, single ended transmission is beneficial with respect to a minimum number of wires and chip area. A detailed comparison of the suitability of both transmission types for wired implantable systems has been performed. A Serial Peripheral Interface connection with Reed Solomon Encoder connection has been implemented. Reed Solomon Error Correction is used to correct the errors occurring on the wired transmission line. Measurements of data rate and error rate for single ended and differential signalling have been performed for long cables (up to 1.8 m). It could be shown that single ended transmission is favourable for the desired application. For the detection and correction of errors occurring on high speed Serial Peripheral Interface Reed Solomon decoding on FPGA was used. This particular decoder design has capability of correcting up to 2 symbol errors on a packet of data composed of 9 symbols where each symbol is 4 bits long. Complete error correction takes about 65 clock cycles on a speed up to 100 MHz.

New data recording plugin for the integration of an integrated circuit for neural recordings into the electrophysiology open source user interface Open Ephys

The research of various diseases like epilepsy or schizophrenia requires an accurate study of bioelectrical signals. An Application Specific Integrated Circuit (ASIC) for the recording of neural signals from neonatal mice was developed [1]. To integrate the developed ASIC into Open Ephys, an open source electrophysiology user interface, a specific plugin is presented. It enables simple configuration of the ASIC, recording of biomedical signals and enables the utilization of many of Open Ephys’ functions. The user interface is well known to neuroscientific researchers and the presented plugin simplifies the use of the integrated circuit for the researchers dramatically. It also enables the use of the ASIC to other kind of applications like neural recordings from mammalians or recordings for brain computer interfaces.

Small area, low power neural recording integrated circuit in 130 nm CMOS technology for small mammalians

In neuroscience research the development of the brain and the treatment of diseases like certain forms of epilepsy is analysed with genetic mouse disease models. For the special case of the recording from neonatal mice a custom designed integrated circuit is presented. Neonatal mice are only two to three centimetres large and have a weight of only a few gram. Thus, the recording circuitry has to be very small and light weight. The integrated circuit implements 16 low-area, low-power analogue differential preamplifiers with a bandpass characteristic (0.5 Hz to 10 kHz). A multiplexed structure of 8:1 multiplexer, post amplifier and 10 bit successive approximation register (SAR) analogue-to-digital converter (ADC) digitizes the signals with high resolution. The digital data is transmitted via a Serial Peripheral Interface (SPI). The integrated circuit has been implemented in a 130 nm CMOS technology and has been successfully applied in in-vivo measurements with an adult mouse.

Integrated 16-Channel Neural Recording Circuit with SPI Interface and Error Correction Code in 130Nm CMOS Technology

In the research of neural diseases like epilepsy and schizophrenia genetic mouse models play a very important role. Dysfunctions during early brain development might cause these diseases. The analysis of the brain signals is the key to understand this process and develop treatments. To enable the acquisition of brain signals from neonatal mice, an integrated circuit for neural recording is presented. It is minimized for low area consumption and can be placed in a miniaturized system on the head of the mouse. It is intended to acquire the local field and action potentials from the brain. 16 analog input channels are implemented. The biomedical signals are amplified with analog pre-amplifiers. Two parallel structures of 8:1 multiplexer, post-amplifier and ADC are implemented to digitize the signals. The post-amplifier has programmable gain and high driving capability. The ADC is implemented as a 10 bit SAR ADC. Digital SPI interfacing is used to reduce the number of transmission lines. Reed Solomon Error Correction Coding has been implemented to enable error correction. The mixed-signal integrated circuit has been successfully implemented in a 130 nm CMOS technology. It is optimized for low area consumption; the channel density is approximately 10 channels/mm².

High speed digital interfacing for a neural data acquisition system - Enabling of live display functionality for a neural recording system

Abstract Diseases like schizophrenia and genetic epilepsy are supposed to be caused by disorders in the early development of the brain. For the further investigation of these relationships a custom designed application specific integrated circuit (ASIC) was developed that is optimized for the recording from neonatal mice [Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. 16 Channel Neural Recording Integrated Circuit with SPI Interface and Error Correction Coding. Proc. 9th BIOSTEC 2016. Biodevices: Rome, Italy, 2016; 1: 263; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider W. Development of a neural recording mixed signal integrated circuit for biomedical signal acquisition. Biomed Eng Biomed Tech Abstracts 2015; 60(S1): 298–299; Bahr A, Abu-Saleh L, Schroeder D, Krautschneider WH. 16 Channel Neural Recording Mixed Signal ASIC. CDNLive EMEA 2015 Conference Proceedings, 2015.]. To enable the live display of the neural signals a multichannel neural data acquisition system with live display functionality is presented. It implements a high speed data transmission from the ASIC to a computer with a live display functionality. The system has been successfully implemented and was used in a neural recording of a head-fixed mouse.