Laith Altimime

The economic impact of EUV lithography on critical process modules

Traditionally, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography be on the forefront of dimensional scaling for the semiconductor industry. Unfortunately, the roadmap for lithography is currently at a juncture of a major paradigm shift. EUV Lithography is steadily maturing but not fully ready to be inserted into HVM. Unfortunately, there are no alternative litho candidates on the horizon that can take over from 193nm. As a result, it is important to look into the insertion point of EUV that would be ideal for the industry from an economical perspective. This paper details the benefit observed by such a transition. Furthermore, it looks into such detail with an EUV throughput sensitivity study.

Enabling 3X nm DRAM: Record low leakage 0.4 nm EOT MIM capacitors with novel stack engineering

We report the lowest leakage achieved to date in sub-0.5 nm EOT MIM capacitors compatible with DRAM flows, showing for the first time a path enabling scalability to the 3X nm node. A novel stack engineering consisting of: 1) novel controlled ultrathin Ru oxidation process, 2) TiO<inf>x</inf> interface layer, is used for the first time to achieve record low Jg-EOT in MIM capacitors using ALD Sr-rich STO high-k dielectric and thin Ru bottom electrode. Record low Jg of 10⁻⁶ A/cm² (10⁻⁸ A/cm²) is achieved for EOT of 0.4 nm (0.5 nm) at 0.8 V. Our data is compared favorably (> 100× Jg reduction at 0.4 nm) to previous best values in literature for MIMcaps with ALD dielectrics.